Optimization and challenges on TSV MEOL integration

Abstract

In the development of emerging 3D IC packaging using TSV, wafer back side treatment is one of key processes. The TSV back side process called MEOL (Middle End Of Line) is a newly introduced process which is performed after front side treatment/bumping, or before chip stacking assembly. The MEOL process adapts some conventional fab processes such dry etch, PECVD, and CMP but there are some differences in the process conditions such as non-mask pattern etch, low temperature deposition of dielectric film, Cu and dielectric film polish and etc [1]. Moreover traditional processes of semi-conductor packaging such as edge trim, wafer back grinding and dicing are also adapted with some modified conditions. For thin wafer handling, wafer temporary bonding and debonding processes are introduced as well. TSV MEOL process consists of the above processes and other supporting ones. These various processes should be aligned or integrated to achieve high yield thru the best optimization. So, it is very important to understand relationship among the processes how they interact each other. This paper is to describe how to optimize every single process with its process monitoring activities in terms of TSV MEOL integration and also some challenges to overcome for volume production of TSV packaging.