Optimization and Implementation of Scaling-Free CORDIC-Based Direct Digital Frequency Synthesizer for Body Care Area Network Systems

Abstract

Coordinate rotation digital computer (CORDIC) is an efficient algorithm for computations of trigonometric functions. Scaling-free-CORDIC is one of the famous CORDIC implementations with advantages of speed and area. In this paper, a novel direct digital frequency synthesizer (DDFS) based on scaling-free CORDIC is presented. The proposed multiplier-less architecture with small ROM and pipeline data path has advantages of high data rate, high precision, high performance, and less hardware cost. The design procedure with performance and hardware analysis for optimization has also been given. It is verified by Matlab simulations and then implemented with field programmable gate array (FPGA) by Verilog. The spurious-free dynamic range (SFDR) is over 86.85 dBc, and the signal-to-noise ratio (SNR) is more than 81.12 dB. The scaling-free CORDIC-based architecture is suitable for VLSI implementations for the DDFS applications in terms of hardware cost, power consumption, SNR, and SFDR. The proposed DDFS is very suitable for medical instruments and body care area network systems.

A low-power and high-SFDR Direct Digital Frequency Synthesizer based on adaptive recoding CORDIC

“…The SFDR of the commercial DDS exceeds the proposed ARC DDS by 3.33dBc, which means that the proposed DDS has less loss in terms of accuracy. However, compared to the latest DDSs based on CORDIC presented in [6] and [7], the SFDR of our proposed ARC DDS exceeds nearly 5dBc. The reason is that ARC reduces the required number of iterations and improves the computation accuracy.…”

“…Tze-Yun Sung et al [6] propose the multiplier-less DDS based on the hybrid CORDIC algorithm to speed up the computation, but it consumes many hardware resources. The DDS architecture presented in [7] adopts the scaling-free (SF) CORDIC [8] algorithm with small ROM to eliminate the scaling factor compensation. However, the architecture is very complex.…”

Simple Hybrid Scaling-Free CORDIC Solution for FPGAs

“…The known methods to improve performance of conventional [1,2,8,9] and scaling-free CORDIC methods [6,7,10,11] are tabular calculation method and the residual method of multiplication described in [4,10,12], respectively. Table method is used to process the most significant bits of the input angle (argument), while the remaining multiplication is for the least significant bits.…”

“…The first method is to create a precalculated table of values for the most significant bits of the computing function argument. In this method [10] proposes an approach based on the scaling-free CORDIC, which combines the functionalities of memory units (LUT) and the corresponding iterative processing. The algorithms [4,12] compute sine and cosine functions, where the first iterations are performed by the classical CORDIC, and then output multipliers are applied, allowing significant savings in hardware resources compared to the classical approach described in [13].…”

“…Methods for transformation of the input angle to the are well known, for example, [8,10], so we will not discuss it here.…”