Optimization based on the minimum maximal k-partial-matching problem of finite states machines with input multiplexing

Abstract

Finite State Machines with Input Multiplexing (FSMIMs) were proposed in previous work as a technique for efficient mapping Finite State Machines (FSMs) into ROM memory. In this paper, we present new contributions to the optimization process involved in the implementation of FSMIMs in Field Programmable Gate Array (FPGA) devices. This process consists of two stages: (1) the simplification of the bank of input selectors of the FSMIM, and (2) the reduction of the depth of the ROM. This has a significant impact both on the number of used Look-Up Tables (LUTs) and on the number of the Embedded Memory Blocks (EMBs) required by the ROM. For the first stage, we present two approaches to optimize FSMIM implementations based on the Minimum Maximal k-Partial Matching (MMKPM) problem: one of them applies the greedy algorithm for the MMKPM problem, and the other based on a new multiobjetive variant of the MMKPM and its corresponding Integer Linear Programing formulation. We also propose a modification of the second stage, in which the characteristics of EMBs are taken into account to improve implementation results. The new optimization process significantly reduces the number of used FPGA resources with respect to the previous one. In addition, the proposed approaches achieve an adequate trade-off between the usage of EMBs and LUTs with respect to conventional FSM implementations based on ROM and to those based on LUT.

A New Approach for Implementing Finite State Machines with Input Multiplexing

“…An approach to generate FSMIMs from FSMs was presented in [15] with the objective of enabling efficient FSMIM implementations in terms of LUT and EMB usage. The Input Selection Matrix (ISM) [10], which can be considered an abstraction of the ISB, is used to describe the optimization problems arising in the generation of FSMIMs.…”

“…Both types of implementation use a combinational circuit, called Input Selector Bank (ISB), to select a different subset of the FSM inputs for each state, allowing for reducing the ROM memory. The optimization process proposed in [15] consists of two stages. In the first one, called Input Selector Simplification (ISS), the ISB is simplified with the aim of saving LUTs (which can also allow it to increase its speed).…”

“…In the first one, called Input Selector Simplification (ISS), the ISB is simplified with the aim of saving LUTs (which can also allow it to increase its speed). The optimization process employed in the ISS stage is modeled as a variant of the Minimum Maximal k-Partial-Matching (MMKPM) problem [16] and solved using an Integer Linear Programming (ILP) formulation [15] or a greedy algorithm [16]. In the second stage, known as State Grouping (SG), the memory depth is further reduced beyond the capabilities of the ISB alone.…”

“…• A new approach to generate FSMIMs from conventional FSMs is proposed with the aim of obtaining further reductions in EMB usage. • Unlike previous approaches [10,15], the SG stage is applied before the ISS stage.…”

“…The ILP formulation proposed in [15] for the ISS stage is extended in order to maintain coherence with the results obtained by the SG stage.…”