Optimization of Additive and Current Conditions for Void-Free Filled Through-Silicon Via

Shin, Se-Hee; Kim, Tea-Yoo; Park, Jong‐Hwan; Suh, Su‐Jeong

doi:10.3390/app8112135

Cited by 14 publications

(11 citation statements)

References 21 publications

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“…The mechanism of multiple additives system has been well reported. [5][6][7] As shown in Fig. 2a, the inhibition additives (suppressor and leveler) occupy the opening region as well as the upper sidewall of the micro via, inhibiting electrodeposition Cu growth, while the accelerator increases the growth rate of electrodeposition Cu in the deep region of the micro via.…”

Section: Resultsmentioning

confidence: 99%

“…Here, suppressors strongly inhibit the growth of Cu in the opening region of the micro via, levelers weakly inhibit the Cu growing on the sidewall, and accelerators slightly increase the growth of Cu in the bottom region. 6 However, as the interaction between these additives is very complicated, the bottom-up filling of micro vias is usually difficult to obtain, and the filling rate of the micro vias is typically slow. 5,7 In recent years, micro vias have been shown to be able to be filled without defects using a single additive (inhibition), indicating a promising approach for the non-defect filling of micro vias using a single additive system.…”

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confidence: 99%

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Communication—Fast Bottom-Up Filling of High Aspect Ratio Micro Vias Using a Single CTAB Additive

Wang

et al. 2020

J. Electrochem. Soc.

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In this study, by adding a single additive of Cetyltrimethyl Ammonium Bromide (CTAB) to the electrolyte, the bottom-up filling of micro via (Φ20 μm × 200 μm) was obtained with a fast filling rate. Accordingly, it was found that CTAB has a better diffusion performance and electrodeposition inhibition effect compared to a typical suppressor and leveler. Moreover, the filling results of the micro vias indicated that CTAB can be transported to the deep region of the micro via, successfully limiting the growth of Cu on the sidewall in these regions.

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Section: Resultsmentioning

confidence: 99%

mentioning

confidence: 99%

Communication—Fast Bottom-Up Filling of High Aspect Ratio Micro Vias Using a Single CTAB Additive

Wang

et al. 2020

J. Electrochem. Soc.

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“…Some researchers reported on additives in the plating solution to simplify and optimize the Cu-filling process. Shin et al [56] optimized the concentration of three chemicals: polyethylene glycol (PEG) as a suppressor, bis-3-(sodiumsulfopropyl disulfide) (SPS) as an accelerator, and Janus Green B (JBG) as a leveler. With the optimized concentration and pulse current, they successfully filled Cu in the TSV with various aspect ratios (2, 2.5, 3) with a depth of 60 µm without defects.…”

Section: Tsv Fillingmentioning

confidence: 99%

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

Cho

Seo

Kim

et al. 2021

Metals

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With the continuous miniaturization of electronic devices and the upcoming new technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation cellular networks (5G), etc., the electronics industry is achieving high-speed, high-performance, and high-density electronic packaging. Three-dimensional (3D) Si-chip stacking using through-Si-via (TSV) and solder bumping processes are the key interconnection technologies that satisfy the former requirements and receive the most attention from the electronic industries. This review mainly includes two directions to get a precise understanding, such as the TSV filling and solder bumping, and explores their reliability aspects. TSV filling addresses the DRIE (deep reactive ion etching) process, including the coating of functional layers on the TSV wall such as an insulating layer, adhesion layer, and seed layer, and TSV filling with molten solder. Solder bumping processes such as electroplating, solder ball bumping, paste printing, and solder injection on a Cu pillar are discussed. In the reliability part for TSV and solder bumping, the fabrication defects, internal stresses, intermetallic compounds, and shear strength are reviewed. These studies aimed to achieve a robust 3D integration technology effectively for future high-density electronics packaging.

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“…Development of the 3D integrated circuit (IC) integration is driven by the demands for further miniaturization of device, higher integration density, lower power consumption and better performance [1][2][3][4]. Si interposer technology is one of the promising solutions for the 3D IC integration which is usually used to stack active chips on a passive Si interposer with through silicon vias (TSVs) as shown in Figure 1a [5,6].…”

Section: Introductionmentioning

confidence: 99%

Preparation and Characterization of High Thermal Conductivity and Low CTE Polyimide Composite Reinforced with Diamond Nanoparticles/SiC Whiskers for 3D IC Interposer RDL Dielectric

Luo

Sun

et al. 2019

Applied Sciences

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Low thermal conductivity and large coefficient of thermal expansion (CTE) are the most serious disadvantages of the polymer dielectric for the interposer redistribution layer (RDL). In this paper, a high thermal conductivity and low CTE composite with polyimide (PI) matrix and diamond nanoparticles/SiC whiskers reinforcement is proposed. The preparation and characterization of the composite film are presented and the effects of the composite on the improvement of the interposer properties are investigated. With 10 wt% diamond-nanoparticles and 7 wt% SiC-whiskers, the composite film has a thermal conductivity of 1.63 W/m·K and a CTE of 16.7 ppm/°C (compared with 0.19 W/m·K and 55.6 ppm/°C of the PI). Interposers with PI RDL dielectric and the composite RDL dielectric are fabricated, respectively. The simulation result shows that the composite dielectric can significantly enhance the properties of the interposer compared with the PI dielectric. The thermal resistance of the interposer decreases from 8.04 °C/W to 1.15 °C/W. The maximum von Mises stress decreases from 72.8 MPa to 16.9 MPa and the warpage decreases from 1.13 μm to 0.15 μm. Thermal distribution tests are performed as well. The results show that the maximum temperature of the interposer decreases from 64 °C to 45.1 °C. The composite developed in this study can reduce the temperature and enhance the reliability of the chips with interposers. It has the potential to expand the application of the interposers in high thermal density integration and high reliability devices.

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Optimization of Additive and Current Conditions for Void-Free Filled Through-Silicon Via

Cited by 14 publications

References 21 publications

Communication—Fast Bottom-Up Filling of High Aspect Ratio Micro Vias Using a Single CTAB Additive

Communication—Fast Bottom-Up Filling of High Aspect Ratio Micro Vias Using a Single CTAB Additive

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

Preparation and Characterization of High Thermal Conductivity and Low CTE Polyimide Composite Reinforced with Diamond Nanoparticles/SiC Whiskers for 3D IC Interposer RDL Dielectric

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