Optimization of Alloy Composition for High-Performance Strained-Si–SiGe N-Channel MOSFETs

Doubling speed using strained Si/SiGe CMOS technology

“…However, the low interface trap density is an indication that Ge diffusion from the virtual substrate has not damaged the gate oxide quality. These results are in good agreement with previously published data which has demonstrated that D it is not significantly degraded until 30% Ge is used in the virtual substrate [3,10]. Long channel devices were used to determine electron and hole effective mobilities (l e,eff , l h,eff ) as a function of vertical effective electric field (E eff ), as shown in Fig.…”

“…1) [3]. While higher channel strain can lead to increased gains in p-channel devices, significant increases in hole mobility are also predicted using a Si 0.75 Ge 0.25 virtual substrate [4].…”

A Quantum Hydrodynamic Simulation of Strained Nanoscale VLSI Device

“…1. According to previous experimental studies [1][2], the effects of interface trap are also considered in the numerical simulation. Fig.…”

“…The introduction of strained Si and SiGe in CMOS technology is a means of improving the performance of Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) in the deep submicron era [1][2]. A general approach to introduce biaxial tensile strain is using a virtual substrate of SiGe [1][2].…”

“…A general approach to introduce biaxial tensile strain is using a virtual substrate of SiGe [1][2]. The underlying SiGe layer serves as an anchor to constrain the lattice of the strained silicon on top.…”