Optimization of Back Channel Leakage Characteristic in PD SOI p-MOSFET

Abstract

The impact of back channel leakage ͑BCL͒ is thoroughly investigated when scaling down partially depleted ͑PD͒ silicon-oninsulator ͑SOI͒ devices. Back channel voltage is introduced as an indicator for monitoring the behavior of BCL. In addition to front-gate devices, back-gate devices also suffer from short channel effect. Finally, BCL can be successfully suppressed by optimizing process parameters such as the Si remains, the well implant, and the SOI thickness.Silicon-on-insulator ͑SOI͒ complementary metal oxide semiconductor ͑CMOS͒ has been widely used in recent years for its better device performance and scalability. Partially depleted ͑PD͒ SOI has a similar device structure to a bulk device. As a consequence, PD SOI can be fabricated using a standard bulk CMOS process. SOI devices have better circuit performance and lower power consumption due to lower channel doping and smaller parasitic capacitances. However, PD SOI devices possess several unique behaviors that do not exist in bulk devices, such as kink effect, 1-3 self-heating effect, 4-6 history delay effect, 7,8 and pass-gate leakage. 9,10 As metaloxide-semiconductor field effect transistor ͑MOSFET͒ sizes are scaled down to the nanoscale regime, leakage current is one of the key challenges faced by designers when attempting to realize devices that provide high performance and high scalability. In PD SOI, there is an additional leakage component other than the common leakage currents of a bulk device, such as junction leakage, gate induced drain leakage, and Drain Induced Barrier Lowering ͑DIBL͒. This leakage component is called back channel leakage ͑BCL͒, which is the subthreshold leakage of a back channel MOSFET. Figure 1 shows the cross section of a PD SOI device with a front-gate channel and a back-gate channel. When the back-gate channel is not turned off properly, BCL can contribute an additional leakage current to the device, resulting in a higher off-state leakage current. Several previous studies are focused on radiation induced BCL. [11][12][13][14][15] It was reported that back-gate bias could suppress the BCL and reduce its impact on circuits. [16][17][18] Consequently, it is important to characterize the BCL behavior and develop a strategy to effectively suppress the BCL.In this paper, the BCL has been characterized by applying a back-gate bias. In the Characterization and Methodology section, we present a methodology for monitoring the BCL. The back-gate device also suffers from the short channel effect ͑SCE͒. In the Results and Discussion section, we discuss the methods used to minimize the BCL of p-MOSFET. Finally, the BCL can be fully controlled in a 45 nm PD SOI process by optimizing three key process parameters: Si remains, well dose, and SOI thickness. Characterization and MethodologyThe devices used in this study are fabricated using a 45 nm SOI process. 19 Figure 2 shows the Id-Vg curves for a p-MOS ͑W/L = 0.6/0.04 um͒ at different back-gate biases ranging from 0 to 30 V. A large subthreshold leakage current occurs when the back-gate ...