Optimization of Bulk Planar Junctionless Transistor using Work function, Device layer thickness and Channel doping concentration with OFF Current constraint

JENIFER, I.; Vinodhkumar, N.; Srinivasan, R.

doi:10.1109/get.2016.7916774

Cited by 4 publications

(4 citation statements)

References 5 publications

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“…This is attributed to the highly doped channel, which increases the scattering effect, thus lowering the mobility [42]. More options are available to the designers in order to optimize the SGJLT; gate work function engineering can lead to an improvement of 29% in the I on /I o f f ratio [41], while a non-uniform (Gaussian) doping concentration through the device layer can reduce the I o f f [43].…”

Section: Single Gatementioning

confidence: 99%

“…This device turned out to be the first one of a new generation of transistors. In the last decades, many other junctionless devices were proposed, which includes FinFET , Gate-All-Around (GAA) [24][25][26][27][28][29][30][31][32][33][34][35][36][37], Single Gate (SGJLT) [38][39][40][41][42][43][44][45][46][47][48][49][50], Double Gate (DGJLT) , Thin Film (TFT) [76][77][78][79][80][81][82][83][84][85][86], and Tunnel FET (TFET) [87][88][89][90][91][92][93][94][95][96][97]. Because most of the review papers on JLTs were published in 2010-2014…”

Section: Introductionmentioning

confidence: 99%

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Junctionless Transistors: State-of-the-Art

2020

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Recent advances in semiconductor technology provide us with the resources to explore alternative methods for fabricating transistors with the goal of further reducing their sizes to increase transistor density and enhance performance. Conventional transistors use semiconductor junctions; they are formed by doping atoms on the silicon substrate that makes p-type and n-type regions. Decreasing the size of such transistors means that the junctions will get closer, which becomes very challenging when the size is reduced to the lower end of the nanometer scale due to the requirement of extremely high gradients in doping concentration. One of the most promising solutions to overcome this issue is realizing junctionless transistors. The first junctionless device was fabricated in 2010 and, since then, many other transistors of this kind (such as FinFET, Gate-All-Around, Thin Film) have been proposed and investigated. All of these semiconductor devices are characterized by junctionless structures, but they differ from each other when considering the influence of technological parameters on their performance. The aim of this review paper is to provide a simple but complete analysis of junctionless transistors, which have been proposed in the last decade. In this work, junctionless transistors are classified based on their geometrical structures, analytical model, and electrical characteristics. Finally, we used figure of merits, such as I o n / I o f f , D I B L , and S S , to highlight the advantages and disadvantages of each junctionless transistor category.

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Section: Single Gatementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Junctionless Transistors: State-of-the-Art

2020

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“…In order to quantify the error of the analytical model, we calculated the RMS error normalized with respect to N D for the concentration of the electrons inside ( RMSi ) and outside ( RMSo ) the depletion region by using the formulas in Equations (8) and (9).…”

Section: Analysis and Simulations Of The Approximated Modelmentioning

confidence: 99%

“…), which allows an improved control on the channel of the transistor. On the other hand, the implementation of two-dimensional (2D) or planar solutions have been recently investigated by numerous researchers because they are simple and easy to fabricate [9][10][11][12]. During the last decade, numerous implementations of junctionless transistors were proposed such as single gate [10,11], double gate [13], thin-film [12], tunnel-FET [14], just to mention a few.…”

Section: Introductionmentioning

confidence: 99%

Analysis of an Approximated Model for the Depletion Region Width of Planar Junctionless Transistors

et al. 2019

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In this paper, we investigate the accuracy of the approximated analytical model currently utilized, by many researchers, to describe the depletion region width in planar junctionless transistors (PJLT). The proposed analysis was supported by numerical simulations performed in COMSOL Multiphysics software. By comparing the numerical results and the approximated analytical model of the depletion region width, we calculated that the model introduces a maximum RMS error equal to 90 % of the donor concentration in the substrate. The maximum error is achieved when the gate voltage approaches the threshold voltage ( V t h ) or when it approaches the flat band voltage ( V F B ) of the transistor. From these results, we concluded that this model cannot be used to determine accurately the flat-band and the threshold voltage of the transistor, although it represents a straightforward method to estimate the depletion region width in PJLT. By using the approximated analytical model, we extracted an analytical formula, which describes the electron concentration at the ideal boundary of the depletion region. This formula approximates the numerical data extracted from COMSOL with a relative error lower than 1 % . The proposed formula is in our opinion, as useful as the formula of the approximated analytical model because it allows for estimating the position of the depletion region also when the drain and source terminals are not grounded. We concluded that the analytical formula proposed at the end of this work could be useful to determine the position of the depletion region boundary in numerical simulations and in graphical representations provided by COMSOL Multiphysics software.

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