Optimization of chip design processes using task graphs

Abstract

The semiconductor industry is characterized by highly progressive and complex products. Fast technological change and improvement lead to increasing complexity of the design process which makes project scheduling and resource management more and more challenging. The variety of influencing factors makes it complicated to predict the main parameters affecting the project success. In our approach a task graph is generated automatically from design process data to clarify the dependencies between the activities. In a second step, the process and the allocation of resources are optimized and evaluated regarding main objectives as time and cost.