Optimization of Conductance Change in Pr1–xCaxMnO3-Based Synaptic Devices for Neuromorphic Systems

Jang, Junwon; Park, Sangsu; Burr, Geoffrey W.; Hwang, Hyunsang; Jeong, Yoon‐Ha

doi:10.1109/led.2015.2418342

Cited by 268 publications

(208 citation statements)

References 9 publications

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“…We applied 30 repeated negative (−4 V, 50 ms) and 30 positive (4 V, 50 ms) gate voltage spikes on ST n (Figure S2, Supporting Information). The synaptic currents of ST50 show the best linearity which benefits learning accuracy in neuromorphic computing networks . We further improve the symmetry of currents by reducing the depressing voltage (2 V, 50 ms) (Figure h).…”

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confidence: 98%

Tunable Synaptic Plasticity in Crystallized Conjugated Polymer Nanowire Artificial Synapses

Han

Guo

et al. 2020

Advanced Intelligent Systems

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In biological synapses, short‐term plasticity is important for computation and signal transmission, whereas long‐term plasticity is essential for memory formation. Comparably, designing a strategy that can easily tune the synaptic plasticity of artificial synapses can benefit constructing an artificial neural system, where synapses with different short‐term plasticity (STP) and long‐term plasticity (LTP) are required. Herein, a strategy is designed that can easily tune the plasticity of crystallized conjugated polymer nanowire‐based synaptic transistors (STs) by low‐temperature solvent engineering. Essential synaptic functions are achieved, such as excitatory postsynaptic current (EPSC), paired‐pulse facilitation (PPF), spike‐frequency‐dependent plasticity (SFDP), spike‐duration‐dependent plasticity (SDDP) and spike‐number‐dependent plasticity (SNDP), and potentiation/depression. The balance between crystallinity and roughness is successfully adjusted by altering solvent compositions, and plasticity of the synaptic device is easily tuned between short term and long term. The evident transition from STP to LTP, good linearity and symmetry of potentiation and depression, and the broad dynamic working range of synaptic weight are achieved. This provides a facile way to tune synaptic plasticity at low temperatures and is applicable to future organic and flexible artificial nervous systems.

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confidence: 98%

Tunable Synaptic Plasticity in Crystallized Conjugated Polymer Nanowire Artificial Synapses

Han

Guo

et al. 2020

Advanced Intelligent Systems

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“…Electron. [50,51] Here, nonlinearity analysis is performed using the previously reported weight update formula: [52] 2020, 6, 1901100 Table 1.…”

Section: Wwwadvelectronicmatdementioning

confidence: 99%

“…[52] The nonlinearity factor calculation was performed on LTP and LTD cycles as depicted in Figure S3, Supporting Information. The α is the nonlinearity factor that controls the potentiation or depression and ω is an internal variable.…”

Section: Hrs L Rs Hrsmentioning

confidence: 99%

Controlled Ionic Tunneling in Lithium Nanoionic Synaptic Transistor through Atomically Thin Graphene Layer for Neuromorphic Computing

Nikam

Kwak

Lee

et al. 2019

Adv Elect Materials

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computers due to the dense neural network of synapses. [3,4] Developing a highspeed and a low-cost artificial synapse device to build an artificial neural network to simulate the human brain like functionalities is the dominant scientific goal of the twenty-first century. Colossal exertion has been committed to developing a synapse device that can trigger the synaptic plasticity and nonvolatility. The conventional neural prototype chip was fabricated based on traditional complementary metal-oxide-semiconductor (CMOS) circuits. [5] However, consumption of high power due to a large number of transistors in COMS circuit limits its further development. [6,7] Besides, a different type of two-terminal memristor such as oxidebased resistive random-access memory (RRAM), [8] ferroelectric memory, [9][10][11][12] and phase-change memory (PCM) [13][14][15] has been employed to mimic the synaptic activity due to reversible analog switching. However, reduced control over conductance change and asynchronous read/write operation limit the application of twoterminal devices as a synaptic element. [16] More recently, a nanoionics synaptic transistor (IST) has been extensively studied and proposed as a suitable candidate for artificial synapses. [17][18][19][20] An IST consists of ionically conducting gate electrolyte and insulating or semiconducting channel. An IST relies on field-driven ion migration from an electrolyte to channel, thereby changing its doping state and hence its conductivity. This device shows reversibility near analog switching, nonvolatility, and low switching energy because of a filamentforming free switching. Additionally, these devices give a high level of accuracy to emulate the synaptic functionalities because synaptic weight update modulated by the gate terminal while the read operation performed on a channel.Recently, several reports show the synaptic behavior by adding and extracting the oxygen (O 2− ) or proton (H + ) in a channel from the electrolyte layer. [17,19,21,22] Both oxygen and proton-based synaptic transistors show unstable behavior and non-linearity due to the structural deformation of a channel as well as the electrolyte layer by mobile H + and O 2− ion. The advantage of using Li + ion in IST is due to more excellent Lithium nanoionic transistors have recently emerged as promising artificial synaptic devices for neuromorphic hardware systems. However, mimicking the essential synaptic functionalities including nonvolatile conductance modulation with a near-linear analog weight update has been a crucial milestone in those synaptic devices and has a direct impact on pattern recognition accuracy. The volatile channel conductance change due to the instability of the solid electrolyte interface and lithium-ion nucleation at electrolyte-channel interface are two key phenomena responsible for the nonlinear switching in lithium nanoionics transistor. Graphene is proposed as an atomically thin ionic tunneling layer to establish nonvolatile analog multilevel conduction in lithium nanoionic transisto...

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“…[5][6][7] In these crossbar arrays, nonvolatile memory (NVM) elements are used to encode synaptic weights. [9][10][11][12] Crossbar arrays have been implemented using a variety of analog NVM elements, including resistive RAM (ReRAM), [13,14] conductive-bridging RAM (CBRAM), [15] flash, [16][17][18][19][20] and phase-change memory (PCM). [8] While the benefits of speed are readily appreciated, enhancement in energy efficiency can be a powerful driver of purchasing decisions in the data center space as well.…”

mentioning

confidence: 99%

Weight Programming in DNN Analog Hardware Accelerators in the Presence of NVM Variability

Mackin

Tsai

Ambrogio

et al. 2019

Adv Elect Materials

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large and unavoidable time and energy penalties for data transport between memory and computational blocks-the so-called "von Neumann" bottleneck.Analog hardware accelerators for deep learning can avoid this bottleneck by performing MAC operations in memory using a crossbar array structure. [5][6][7] In these crossbar arrays, nonvolatile memory (NVM) elements are used to encode synaptic weights. This was recently shown capable of 280× speedup in per area throughput while also providing 100× enhancement in per area energy efficiency over state-of-the-art GPUs. [8] While the benefits of speed are readily appreciated, enhancement in energy efficiency can be a powerful driver of purchasing decisions in the data center space as well. [9][10][11][12] Crossbar arrays have been implemented using a variety of analog NVM elements, including resistive RAM (ReRAM), [13,14] conductive-bridging RAM (CBRAM), [15] flash, [16][17][18][19][20] and phase-change memory (PCM). [21,22] However, most NVM device candidates exhibit varying extents of nonideal behavior, including limited resistance contrast, significant nonlinearity in conductance change, as well as strong asymmetry in bidirectional programming. At the application level, this manifests into neural network accuracies that are significantly lower than software-based approaches. Many of these nonidealities, however, can be addressed to an extent through device and circuit-level engineering. One key idea is multiple conductances of varying significance (Figure 1a), where each synaptic weight is distributed across at least two conductance pairs using W = F(G + − G − ) + (g + − g − ). For instance, during training, such a PCM cell could be paired with a capacitive cell to combine complementary features of both and relax the overall device requirements on PCM. [8] In such a scheme, the majority of DNN weight tuning can occur on a linear but volatile 3T1C memory structure, with periodic but infrequent transfer to the PCM cell for nonvolatile storage. Row-(or column-)wise weight transfer also arises in ex situ training and other training variants. Since PCM is subject to the previously mentioned nonidealities, this weight transfer is best performed with a closed-loop iterative tuning procedure with multiple write-plus-read-verify steps to achieve the overall target weight. To avoid performance degradation, particularly during training, NVM programming Crossbar arrays of nonvolatile memory (NVM) can potentially accelerate development of deep neural networks (DNNs) by implementing crucial multiply-accumulate (MAC) operations at the location of data. Effective weight-programming procedures can both minimize the performance impact during training and reduce the down time for inference, where new parameter sets may need to be loaded. Simultaneous weight programming along an entire dimension (e.g., row or column) of a crossbar array in the context of forward inference and training is shown to be important. A framework for determining the optimal hardware conditions in which to program w...

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Optimization of Conductance Change in Pr_1–xCa_xMnO₃-Based Synaptic Devices for Neuromorphic Systems

Cited by 268 publications

References 9 publications

Tunable Synaptic Plasticity in Crystallized Conjugated Polymer Nanowire Artificial Synapses

Tunable Synaptic Plasticity in Crystallized Conjugated Polymer Nanowire Artificial Synapses

Controlled Ionic Tunneling in Lithium Nanoionic Synaptic Transistor through Atomically Thin Graphene Layer for Neuromorphic Computing

Weight Programming in DNN Analog Hardware Accelerators in the Presence of NVM Variability

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