Optimization of Delay and Energy in On-Chip Buses using Bus Encoding Technique

Abstract

In very deep sub-micron (VDSM) fault-tolerant busses, crosstalk noise and logic faults caused due to shrinking wiresize and reduced inter-wire spacing are major factors affecting the performance of on-chip interconnects, such as high power consumption and increased delay. In this paper we propose a bus optimization technique which reduce the energy and power-delay using Hamming Single Error Correcting Code. In this coding scheme we implement Fibonacci representation of optimal (7,4) Hamming Code which is more efficient than Single Error correction (9,4) Hamming Code. Also the proposed scheme eliminates crosstalk classes among the interconnects wires, there by reducing delay and energy consumption. The proposed techniques achieves an efficiency of 11% in energy consumption and a reduction of delay with respect to the existing techniques.