Optimization of Design Space for Vertically Stacked Junctionless Nanosheet FET for Analog/RF Applications

For the first time, a nanosheet field effect transistor (NS FET) performance is demonstrated by incorporating various device engineering at both device and circuit levels. Various device topologies like lightly-doped drain/source, underlap, single and dual-k spacer are explored and the performance is compared with conventional NS FET. The NS FET with dual-k spacer is able to reduce the off current by 13.6× compared to the traditional NS FET. Further, the dual-k spacer offered good electrostatic performance and high switching ratio. Moreover, the analog/RF figures of merit are assessed for various device configurations. Though the dual-k spacer outperforms in terms of DC and analog metrics, the conventional NS FET can offer better RF metrics owing to the high current. Further, circuit level analysis is carried out using the Cadence tool for mixed circuit applications. The crucial circuits for IC design such as inverter, ring oscillator and common source (CS) amplifier are designed and evaluated the performance. The NS FET with dual-k spacer offers a gain of 1.815 for the CS amplifier and an oscillation frequency of 34.09 GHz for the 3-stage ring oscillator. The results will give insights into the performance of NS FET with various device architectures

Section: And Analog/rf Analysismentioning

confidence: 99%

Spacer Engineering on Nanosheet FETs towards Device and Circuit Perspective

Kumari,

Sreenivasulu,

Ajayan

et al. 2023

“…Hence, to tackle this issue uniform doping across all the regions (source/drain/channel) is adopted (nothing but a junctionless (JL) structure) to simplify the fabrication process and thermal budgets. 31 The low thermal budget of JLFET allows the device engineers to have more leeway when choosing GS materials. 32 The reduced process flow is also one of the main advantages of JLFET due to the ease of fabrication steps.…”

mentioning

confidence: 99%

Design and Performance Optimization of Junctionless Bottom Spacer FinFET for Digital/Analog/RF Applications at Sub-5nm Technology Node

Valasa¹,

Kotha²,

Narendar³

et al. 2023

Self Cite

This article for the first time reports the design and performance optimization of Junctionless (JL) Bottom spacer (BSP) FinFET. Initially to get the desired value of workfunction (∅_m) and fin thickness (Tfin) for analog/RF analysis, the optimization of these parameters has been done by considering several values. It has been noticed that the increase in ∅_m and reduction in Tfin can lead to better electrical performance with suppressed short channel effects (SCE). Further, it is also observed that reduction in bottom spacer height (HBSP) can fetch enhanced analog/RF performance considering the improvement noticed in transconductance (gm), intrinsic gain (AV), transconductance generation factor (TGF), cutoff frequency (fT), and Gain frequency product (GFP). Moreover, when the bottom spacer dielectric permittivity (KBSP) is increased from 3.9 to 22, it has been found that the analog/RF performance degrades significantly.

“…These effects lead to various short channel effects (SCEs) like degradation of subthreshold swing (SS), drain induced barrier lowering (DIBL), gate leakages, threshold voltage roll-off, etc. [7][8][9] With advancements in scaling, various device engineering, such as gate dielectric engineering, gate material engineering, device engineering, channel engineering, etc, came into existence to reduce to SCEs. [10][11][12] Multiple gate architectures like Double Gate (DG), Trigate, FinFET, and gate all around (GAA) FETs are proposed to overcome SCEs.…”

mentioning

confidence: 99%

Gate Stack Analysis of Nanosheet FET for Analog and Digital Circuit Applications

Kumari,

Vijayvargiya,

Upadhyay

et al. 2023

This manuscript demonstrates the performance comparison of vertically stacked nanosheet FET with various high-k materials in gate stack (GS) configuration. As the high-k dielectric materials are inevitable to continual scaling, in this paper, various high-k dielectric materials such as Si3N4, Al2O3 and HfO2 are incorporated in the GS, and the performance is studied. Further, DC and Analog/RF performance metrics are discussed in detail, and it is noticed that by using HfO2 in high-k GS, the on current (I ON) is enhanced by 46.7% and off current (I OFF) is decreased by 81.6% as compared to conventional NSFET (C-NSFET) without high-k GS. Also, the switching ratio (I ON/I OFF) is increased by 8× from SiO2 to HfO2, ensuring good logic applications. Moreover, compared to the C-NSFET, GS-NSFET with HfO2 offers better values for analog metrics like transconductance (gm) and transconductance generation factor (TGF). However, as the k value increases, the capacitances are also observed to be increased. As a result, the intrinsic delay (τ) increases by 9%, 6% and 20% from SiO2 to Si3N4, Si3N4 to Al2O3, Al2O3 to HfO2, respectively. On top of that, the circuit level demonstration is also performed for resistive load based inverter and ring oscillator (RO) for both C-NSFET GS NSFET with HfO2 as GS material. From circuit analysis, it is observed that by using the GS, the performance of the inverter is increased in terms of noise margins and DC gain. However, the oscillation frequency (f OSC) of 3-stage RO is decreased by 14.7% with the incorporation of GS owing to the increment in gate capacitance (Cgg). Consequently, the results will give deep insights into the performance analysis of NSFET with various high-k materials in gate stack at both device and circuit levels.