2001 IEEE Nuclear Science Symposium Conference Record (Cat. No.01CH37310)
DOI: 10.1109/nssmic.2001.1009297
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Optimization of front-end design in imaging and spectrometry applications with room temperature semiconductor detectors

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Cited by 3 publications
(5 citation statements)
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“…Equation (10) shows that 1 noise gives an ENC contribution dependent on the peaking time, if . From (10), an effective evaluation of ENC when the gate width is scaled to match the detector capacitance is provided by the normalized spectral density [6] (11) Fig. 8 compares the product of 0.18 m NMOS from two foundries.…”
Section: Effect Of Noise In Charge Measurementsmentioning
confidence: 99%
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“…Equation (10) shows that 1 noise gives an ENC contribution dependent on the peaking time, if . From (10), an effective evaluation of ENC when the gate width is scaled to match the detector capacitance is provided by the normalized spectral density [6] (11) Fig. 8 compares the product of 0.18 m NMOS from two foundries.…”
Section: Effect Of Noise In Charge Measurementsmentioning
confidence: 99%
“…The scaling acts also in reducing the thickness of the gate oxide to a few nanometers, which results in a remarkable improvement in radiation hardness features of the CMOS processes. This makes these technologies suitable for rad-hard front-end design [6] in space and high-energy physics applications, if enclosed layout techniques are used to mitigate leakage current contributions [7]. However, it is very important to monitor how process parameters are influenced by scaling, especially with respect to noise, which can be affected by gate oxide quality and short channel phenomena.…”
Section: Introductionmentioning
confidence: 99%
“…All circuits have a cascoded PMOS input, because PMOS transistors achieve a good trade-off between white and 1/f noise [2], [3]. They are named by letters A, B, C and D. Here is a short description of each of them:…”
Section: Circuit Designmentioning
confidence: 99%
“…For medical imaging systems, the main constraint is to insure high integration density and low power. But for both applications, low noise is required and thus global optimization of the performance will require making various trade-offs [1]- [3].…”
Section: Introductionmentioning
confidence: 99%
“…Perhaps even more importantly, it acted also in the sense of reducing the thickness of the gate oxide to a few nanometers. The result of a shorter gate and a thinner gate oxide is a remarkable improvement in noise and radiation hardness features of the CMOS processes, such to make them fully adequate for front-end design [6,7].…”
Section: Introductionmentioning
confidence: 99%