Proceedings of International Electron Devices Meeting
DOI: 10.1109/iedm.1995.499381
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Optimization of high Q integrated inductors for multi-level metal CMOS

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Cited by 64 publications
(27 citation statements)
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“…Further reduction in area is achieved using three-dimensional structures [10]. These structures benefit from strong mutual coupling between vertically adjacent metal layers, and can generate the same inductance in less area as compared with planar inductors.…”
Section: Stacked Inductorsmentioning
confidence: 99%
“…Further reduction in area is achieved using three-dimensional structures [10]. These structures benefit from strong mutual coupling between vertically adjacent metal layers, and can generate the same inductance in less area as compared with planar inductors.…”
Section: Stacked Inductorsmentioning
confidence: 99%
“…This approach considerably reduces the area of the system. However, by using a standard CMOS fabrication process, passive inductors usually have small inductance (typically in the range of nanohenries [23]) and high resistance, leading to quality factors with maximum value at high frequency (from hundreds megahertz up to few gigahertz) and usually lower than 10 [24], [25]. For these reasons, this approach is not suitable for power links operating in the low megahertz range.…”
Section: Design Techniques For Inductive Linksmentioning
confidence: 99%
“…After multiplying (9) and (10) by , calculating the integral over from 0 to , and using (13a) and (13b), one arrives at (14) (15) Here, the integrations are carried out over the cross sections of the rings in the --plane (perpendicular to the azimuthal unit vector ), , and…”
Section: B Quasi-one-dimensional (1-d) Approximationmentioning
confidence: 99%