Optimization of microfluidic layouts as a wired packing problem

Andriamiseza, Sanjy; Trellet, Mikaël; Lafitte, Nicolas; Clerget, Charles-Henri; Petit, Nicolas

doi:10.1016/j.ifacol.2021.08.296

IFAC-PapersOnLine

2021

DOI: 10.1016/j.ifacol.2021.08.296

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Optimization of microfluidic layouts as a wired packing problem

Sanjy Andriamiseza

Mikaël Trellet

Nicolas Lafitte

et al.

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2023

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Two-dimensional Device Layout and Wiring by Hierarchical Optimization

Tanimura,

Azuma,

Takano

et al. 2023

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Two-dimensional layout problem is studied to minimize the wiring cost by optimal layout of the devices and wiring path connecting the devices. The present study divides the problem into a parent problem of device layout and a child problem of wiring under the given device layout and repeats to solve each problem iteratively. The decision variables of device layout are mixed with discrete variables for the direction and continuous variables for the location. Therefore, the location is discretized as target points, and each device is located at the point nearest to the given target point under the given constraints. Computer experiments are conducted to show the effectiveness of the proposed method, where simulated annealing is applied to a device layout and particle swarm optimization is applied to a wiring problem. Moreover, it is observed that the directions of the devices are gradually fixed in the descending order of the device size during the search, and the interval of the target points as the discretization size does not significantly affect the quality of the obtained solution, which is considered to be caused by the given constraints and a translational symmetry in the total wiring length under the present geometric constraints.

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Two-dimensional Device Layout and Wiring by Hierarchical Optimization

Tanimura,

Azuma,

Takano

et al. 2023

Transactions of ISCIE

View full text Add to dashboard Cite

show abstract

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Optimization of microfluidic layouts as a wired packing problem

Cited by 1 publication

References 22 publications

Two-dimensional Device Layout and Wiring by Hierarchical Optimization

Two-dimensional Device Layout and Wiring by Hierarchical Optimization

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