Optimization of NULL convention self-timed circuits

Smith, Scott C.; DeMara, Ronald F.; Yuan, J.S.; Ferguson, D.; Lamb, D. R.

doi:10.1016/j.vlsi.2003.12.004

Cited by 83 publications

(53 citation statements)

References 22 publications

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“…The principle of transistor-level threshold gate design can be found in [7]. The design of computational blocks, registers and completion detection blocks using threshold gates is available in [8]. For example, a dual-rail NCL full adder can be optimized as Fig.…”

Section: Null Convention Logicmentioning

confidence: 99%

Soft error in FPGA-implemented asynchronous circuits

Kuang¹,

Bai²

2011

2011 VII Southern Conference on Programmable Logic (SPL)

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In this paper, we investigate the mechanism of soft error generation and propagation in asynchronous circuits which are implemented on FPGAs. The effects of the soft errors on Quasi-delay-insensitive (QDI) asynchronous circuits are analyzed. The results show that �� easier to detect the soft error in asynchronous circuits implemented on FPGAs so that FPGAs can be reprogrammed, compared with traditional synchronous circuits.

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Section: Null Convention Logicmentioning

confidence: 99%

Soft error in FPGA-implemented asynchronous circuits

Kuang¹,

Bai²

2011

2011 VII Southern Conference on Programmable Logic (SPL)

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“…Two strategies have been proposed: (i) optimizing every gate, but adding local completion detectors [1], [4], [10], and (ii) optimizing only some of the gates, with no added local completion detectors [16]. In the first strategy, all gates are relaxed to speed up computation, but local detectors are used to ensure robust completion.…”

Section: C-4mentioning

confidence: 99%

“…Asynchronous design has been the focus of renewed interest and research activity because of the potential benefits of low power consumption, low electromagnetic interference, robustness to parameter variations, and modularity of designs [20]. As an example, Theseus Logic developed an asynchronous version of the Motorola CPU08 microcontroller as part of the MCORE project and reported 40% less power and 10dB less peak EMI noise than Motorola's synchronous version [13], [16]. Also, in recent work at Seiko/Epson, Karaki [9] demonstrated that asynchronous design is an effective approach for dealing with high variability of delays, when building flexible LTPS (Low Temperature Poly Silicon) TFT (Thin Film Transistor) displays.…”

Section: Introductionmentioning

confidence: 99%

Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation

Jeong

Nowick

2007

2007 Asia and South Pacific Design Automation Conference

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Abstract-As process, temperature and voltage variations become significant in deep submicron design, timing closure becomes a critical challenge using synchronous CAD flows. One attractive alternative is to use robust asynchronous circuits which gracefully accommodate timing discrepancies. However, these asynchronous circuits typically suffer from high area and latency overhead. In this paper, an optimization algorithm is presented which reduces the area and delay of these circuits by relaxing their overly-restrictive style. The algorithm was implemented and experiments performed on a subset of MCNC circuits. On average, 49.2% of the gates could be implemented in a relaxed manner, 34.9% area improvement was achieved, and 16.1% delay improvement was achieved using a simple heuristic for targeting the critical path in the circuit. This is the first proposed approach that systematically optimizes asynchronous circuits based on the notion of local relaxation while still preserving the circuit's overall timing-robustness.

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“…The next conversion may then occur. The combinational logic circuitry is derived using the Threshold Combinational Reduction (TCR) methodology [6] that employs truth tables, karnaugh maps or a NCL logic minimization program to generate the expressions. Once the expressions have been derived, they must be checked for completeness of input to ensure delay insensitivity.…”

Section: Combinational Logicmentioning

confidence: 99%

“…Delays are added based on worst-case scenarios to avoid 2 T. Kocak, G. Harris, R. DeMara hazard conditions. This leads to extensive timing analysis of worst-case behavior to ensure correct circuit operation 9 . Self-timed designs have demonstrated higher application-level throughput since average case delay is less than that of synchronous circuits which are designed to accomodate the worst-case propagation delays 18 19 .…”

Section: Introductionmentioning

confidence: 99%

Self-Timed Architecture for Masked Successive Approximation Analog-to-Digital Conversion

Koçak

Harris

DeMara

2007

J CIRCUIT SYST COMP

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In this paper, a novel architecture for self-timed analog-to-digital conversion is presented, designed using the NULL Convention Logic (NCL) paradigm. This analog-to-digital converter (ADC) employs successive approximation and a one-hot encoded masking technique to digitize analog signals. The architecture scales readily to any given resolution by utilizing the one-hot encoded scheme to permit identical logical components for each bit of resolution. The 4-bit configuration of the proposed design has been implemented and assessed via simulation in 0.18-µm CMOS technology. Furthermore, the ADC may be interfaced with either synchronous or four-phase asynchronous digital systems.

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Optimization of NULL convention self-timed circuits

Cited by 83 publications

References 22 publications

Soft error in FPGA-implemented asynchronous circuits

Soft error in FPGA-implemented asynchronous circuits

Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation

Self-Timed Architecture for Masked Successive Approximation Analog-to-Digital Conversion

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