Optimization of operation temperature of gate commutated thyristors for hybrid DC breaker

Lyu, Gang; Liu, Jiapeng; Zhang, Wenpeng; Zeng, Rong; Zhang, Xueqiang; Palmer, P.R.

doi:10.1109/ecce.2017.8096663

Cited by 5 publications

(5 citation statements)

References 12 publications

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“…This topology benefits from many advantages: there is no central capacitor on the DC link which avoids fast and dangerous discharge of energy in case of short‐circuits [27]; arm inductors limit d i /d t and reduce short‐circuit currents [28]; the topology's modularity makes the mechanical assembly easier, even for a large number of levels and it also allows the use of identical components, thus reducing production and maintenance costs [29]. In an IGCT cell, a d i /d t choke and a clamp circuit are necessary to limit diode reverse‐recovery current during IGCT turn‐on [30] and fault current in the case of semiconductor failure [31].…”

Section: Hvdc Link and Convertersmentioning

confidence: 99%

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Selection of an IGCT for multilevel converters dedicated to high‐voltage direct current grid connection of offshore wind‐farms

Ladoux

Sanchez

Cornet

et al. 2021

IET Power Electronics

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Grid connection of remote offshore wind-parks uses high-voltage direct current technology and in order to reduce costs and losses and maximise profitability, semiconductor power losses must be minimised. To properly choose the semiconductors, it is necessary to estimate their losses for a large number of operating conditions. This article deals with a modelling approach to calculate power losses for many such operating conditions, based on measured semiconductor characteristics and the chosen multilevel modulation strategy. The case of the integrated gate-commutated thyristor is considered because, for a given device rating, it is possible to select an integrated gate-commutated thyristor benefiting from the best trade-off between on-state losses and turn-off losses, thus minimising the power losses of the two end-stations.

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Section: Hvdc Link and Convertersmentioning

confidence: 99%

“…In an IGCT cell, a di/dt choke and a clamp circuit are necessary to limit diode reverse-recovery current during IGCT turn-on [30] and fault current in the case of semiconductor failure [31].…”

Section: Presentationmentioning

confidence: 99%

Selection of an IGCT for multilevel converters dedicated to high‐voltage direct current grid connection of offshore wind‐farms

Ladoux

Sanchez

Cornet

et al. 2021

IET Power Electronics

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“…The voltage drop across the N‐buffer region comprises two components: the voltage drop across J1 and the voltage drop across the boundary of the N‐buffer region adjacent to the CSR

({, \begin{aligned} V_{J 1} = V_{normalt} \ln ()(, \frac{p_{b 1} N_{Nb}}{n_{normali}^{2}}) \\ V_{Nb} = V_{J 1} + V_{normalt} \ln ()(, \frac{N_{normalB}}{N_{normalB} + p_{x 1}}) \end{aligned})

The gated drive is simplified by applying a DC voltage source connected in series with a resistor and an inductor, of which the value is 0.08 mΩ and 2.15 nH, respectively [12].…”

Section: Model Of the High‐power Igct With Multiple Physical Effectsmentioning

confidence: 99%

“…However, the Levels 0–2 models are too simple, leading to the poor prediction of switching behaviours. The IGCT models in the Levels 4 and 5 [12] are two‐dimensional (2D) or 3D models developed in finite element model (FEM) tools. They are the most accurate models but great central process unit (CPU) capacity is required.…”

Section: Introductionmentioning

confidence: 99%

“…The Level 3 models are physics‐based compact models with accurate characteristics within SOA and acceptable CPU capacity. So the Level 3 models are suitable for circuit design optimisation where the prediction of the IGCT’ electrical characteristics is required such as switching loss and voltage overshoot during turning off [12]. In addition, with the acceptable CPU capacity requirement, the Level 3 models can also be used to simulate the whole GCT wafer where optimisation of the layout of GCT wafer can be fulfilled.…”

Section: Introductionmentioning

confidence: 99%

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Physics‐based compact model of integrated gate‐commutated thyristor with multiple effects for high‐power application

Lyu

Zhuang

Li³

et al. 2018

IET Power Electronics

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This paper presents a physics-based compact model of integrated gate-commutated thyristor (IGCT) with multiple effects for high power application. The proposed model has both acceptable accuracy and computation time requirement, which is suitable for system level circuit simulation and IGCT's whole wafer modelling work. First, the development of IGCT model is discussed and the one-dimension phenomenon of IGCT is analyzed in the paper. Second, a physics-based compact model of IGCT is proposed. The proposed model of IGCT includes multiple physical effects that are crucial to IGCTs working in high power applications. These physical effects include the impact ionization effect, moving boundary of depletion region during punch-thourgh (PT) and the local lifetime region. The Fourier series solution is applied for the ambipolar diffusion equation in the base region. Third, the proposed model is implemented in Simulink and compared with the model in Silvaco Atlas, a finite-element (FEM) tool. Finally, the proposed compact model of IGCT is validated by experiments. Keywords-physics-based compact model, local lifetime region, gate commutated thyristors, punch through, power semiconductor modeling NOMENCLATURE A Total active area. (cm 2) q Electric charge (J) Si Dielectric constant for silicon. (F/cm 2) k Boltzmann's constant. (J/K) T Absolute temperature. (K) Vt=kT/q Thermal Voltage. (V) n0 Electron mobility. (cm 2 /Vs) p0 Hole mobility. (cm 2 /Vs) D Ambipoar diffusivity. (cm 2 /s) Dn Electron diffusivity. (cm 2 /s) Dp Hole diffusivity. (cm 2 /s) h Recombination parameter. (cm 2) J Current density. (A/cm 2) In1,Ip1 Electron and hole current at x1 edge of undepleted drift region. (A) In2,Ip2 Electron and hole current at x2 edge of undepleted drift region. (A) IA Total anode current. (A) IC Total cathode current. (A) IG Total gate current. (A) NB N-base region doping concentration. (cm-3) NPb P-base region doping concentration. (cm-3) NNb N-base region doping concentration. (cm-3) ni Intrinsic carrier concentration. (cm-3) n Electron carrier concentration. (cm-3) p Hole carrier concentration. (cm-3) px1 Hole carrier density at x1. (cm-3) px2 Hole carrier density at x2. (cm-3) t Time. (s) HL High-level lifetime. (s) LL Low-level lifetime. (s) Vd Voltage across depletion region. (V) W Thickness of stored charge region. (cm) WB Thickness of N-base region. (cm) WN+ Thickness of N-base region. (cm) WPb Thickness of P-base region. (cm) WNb Thickness of N-buffer region. (cm) IET Review Copy Only IET Power Electronics This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication in an issue of the journal. To cite the paper please use the doi provided on the Digital Library page.

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Power Electronics Based High-Speed Switching Module for 1500 V dc Traction Rectifier Stations

Ahmad¹

2022

2022 IEEE 1st Industrial Electronics Society Annual on-Line Conference (ONCON)

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Optimization of operation temperature of gate commutated thyristors for hybrid DC breaker

Cited by 5 publications

References 12 publications

Selection of an IGCT for multilevel converters dedicated to high‐voltage direct current grid connection of offshore wind‐farms

Selection of an IGCT for multilevel converters dedicated to high‐voltage direct current grid connection of offshore wind‐farms

Physics‐based compact model of integrated gate‐commutated thyristor with multiple effects for high‐power application

Power Electronics Based High-Speed Switching Module for 1500 V dc Traction Rectifier Stations

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