Optimization of scannable latches for low energy

Abstract

Abstract-This paper covers a range of issues in the design of latches and flip-flops for low-power applications. First it revisits, extends, and improves the energy-performance optimization methodology, attempting to make it more formal and comprehensive. The data-switching factor and the glitching activity are taken into consideration, using a formal analytical approach, then a notion of an energy-efficient family of configurations is introduced to make the comparison of different latch styles in the energy-performance space more fair. A recently proposed methodology for balancing hardware intensity in processor pipelines is applied to latch design to facilitate the selection of the objective function for tuning transistor sizes. The power dissipation of the clock distribution is taken into account, supported by simulations of extracted netlists for multibit datapath registers. Practical issues of building a low overhead scan mechanism are considered, and the power overhead of the scannable design is analyzed. A low-power level-sensitive scan mechanism is proposed, and results of a comparative study of scannable latches are shown. The applicability of the proposed scan mechanism to a wide variety of latches is demonstrated.

The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements

“…Since the optimum break-up conditions are unknown in advance, we propose to extend this work to address the most important question in the design of the clocked storage elements: given the application and the set of candidate storage elements, what is the best choice of the CSE topology and what is its optimal design point in terms of transistor sizing? In subsequent works, Zyuban [7] proposes comparing the CSEs based on energy efficient characteristics with fixed input size and output load which is a significant improvement versus metric-based comparisons. However, this work does not capture the effect of the loading conditions on the CSE comparison which is necessary for determining the Energy and Delay break-up between CSEs and logic.…”

“…This paper presents a comparison and analysis of the CSEs based on their energy-delay characteristics and a particular application. The notion of CSE performance is extended by using the composite energy-delay characteristics over an entire collection of CSEs [7] and by formulating the natural target application of each individual CSE. A quantitative method for optimal cycle time break-up is defined on the system level and based on practical environment and system parameters constraints, that is, the combined effect of the varying delay target for the CSE and varying CSE load due to the changing operating point of the logic block with the target cycle time must be accounted for to achieve a meaningful quantitative analysis.…”

Flip-Flop Design in Nanometer CMOS

“…According to [153,157,158], the value j=i (g) is named "hardware intensity". Basically, j=i (g) quantifies the effort to be spent in sizing a circuit to optimize the speed of the circuit at the expense of its energy consumption.…”

Variability of flip-flop timing at sub-threshold voltages

“…Sub-threshold systems are typically used for nontiming critical applications aiming an operation at the minimum energy point, thus the voltage where further reduction in supply voltage would result in an increase in energy per operation due to an increased leakage component [7]. As opposed to most other circuit optimization approaches [10,2] here the optimization goal in transistor sizing thus only is an energy and no energy-delay-product optimization. Considering only active energy, the optimum therefore obviously is the configuration where all transistors have minimum width.…”