Optimization of Small-Delay Defects Test Quality by Clock Speed Selection and Proper Masking Based on the Weighted Slack Percentage

Hasib, Omar Al-Terkawi; Savaria, Yvon; Thibeault, Claude

doi:10.1109/tvlsi.2019.2949037

Cited by 9 publications

(9 citation statements)

References 35 publications

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“…Normal scan test employs a lower clock frequency, aiming to verify the correctness of the chip's logic functionality. In contrast, the at-speed test utilizes a testing frequency consistent with the chip's working frequency to detect internal delay faults [11], ensuring normal operation at the set frequency. To enhance test quality and detect minor delay faults, a faster-than-at-speed test uses a testing frequency higher than the chip's working frequency.…”

Section: Dft and Related Work 21 Scan Test Designmentioning

confidence: 99%

FATE: A Flexible FPGA-Based Automatic Test Equipment for Digital ICs

Zhang,

Liu,

et al. 2024

Electronics

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The limits of chip technology are constantly being pushed with the continuous development of integrated circuit manufacturing processes and equipment. Currently, chips contain several billion, and even tens of billions, of transistors, making chip testing increasingly challenging. The verification of very large-scale integrated circuits (VLSI) requires testing on specialized automatic test equipment (ATE), but their cost and size significantly limit their applicability. The current FPGA-based ATE is limited in its scalability and support for few test channels and short test vector lengths. As a result, it is only suitable for testing specific chips in small-scale circuits and cannot be used to test VLSI. This paper proposes a low-cost hardware and software solution for testing digital integrated circuits based on design for testability (DFT) on chips, which enables the functional and performance test of the chip. The solution proposed can effectively use the resources within the FPGA to provide additional test channels. Furthermore, the round-robin data transmission mode can also support test vectors of any length and it can satisfy different types of chip test projects through the dynamic configuration of each test channel. The experiment successfully tested a digital signal processor (DSP) chip with 72 scan test pins (theoretically supporting 160 test pins). Compared to our previous work, the work in this paper increases the number of test channels by four times while reducing resource utilization per channel by 37.5%, demonstrating good scalability and versatility.

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Section: Dft and Related Work 21 Scan Test Designmentioning

confidence: 99%

FATE: A Flexible FPGA-Based Automatic Test Equipment for Digital ICs

Zhang,

Liu,

et al. 2024

Electronics

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“…The former phase uses the already available delay table and the smallest effective slack information to generate the test clock data set and the latter phase selects the most optimal data points (test clock periods) from the data set based on the number of constraints on the test clock periods. The selected data is completely dependent on the circuit characteristics rather than a hit-or-miss technique as in [24]. The selected clock periods including the system clock period are given as input to the test optimization phase to generate the optimized SDD test options.…”

Section: Workflowmentioning

confidence: 99%

“…Hence, the user-defined value N (maximum number of test clock periods that can be used) is set. The number of clock periods selected should be less than or equal to N. In this work, N is considered to be 4 to compare with the work in [24]. The impact of the…”

Section: B Selection Of Optimal Test Clock Periodmentioning

confidence: 99%

“…Testing a defect less than SEDD size will result in overtesting of the circuit. A method that considers the masking concept, predefined frequencies, and quality metric to generate optimal test options (proper combination of test clock, pattern, endpoint mask) is proposed in [24]. Here, instead of pattern delay information the multiples of the system clock period are used as test clocks.…”

Section: Introductionmentioning

confidence: 99%

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Optimal Test Clock Frequency Based Test Option Generation for Small Delay Defects

Muthukrishnan,

Sathasivam

2023

IEEE Access

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Small delay defects (SDD) based test escapes are caused by the nature of transition delay fault (TDF) ATPG, which propagates the fault effect along the shorter path in the interest of run time. However, owing to the benefits of a lesser pattern count and complexity, TDF ATPG is the most feasible option for delay testing. Faster than at-speed testing enhances the likelihood of detecting SDD. To generate the optimal test option and prevent over or under-testing the circuit, it is necessary to select the appropriate test clock period. The recently introduced Weighted slack percentage (WeSPer) metric is used in this article to identify the best SDD test option. The method's benefit is combined with the proper selection of the optimal clock frequency to test the SDD. This article proposes an optimal test clock period selection method by considering the size of the smallest possible delay defect size that can fail the circuit during at-speed operation and the fault's propagation delay. The proposed method is applied to the set of ISCAS89 and ITC99 benchmark circuits to evaluate its effectiveness.INDEX TERMS Faster-than-at-speed testing, fault models, nanoscale devices, small delay defects, test quality metric, VLSI testing.

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“…The AnARM was fabricated with a 28 nm technology, as reported in [9]. It first served as a proof of concept to be compared with other general-purpose processors and provided a context for a novel self-timed cache architecture [10], a new model for dynamic voltage scaling [11], and original test methods [12]. We revisit the original Octasic self-timed design style using circuits and methods coming from the asynchronous literature, with the objective of lowering the barrier with timing-driven EDA flows.…”

Section: Introductionmentioning

confidence: 99%

Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow

Fiorentino

Thibeault

Savaria

2021

IET Computers & Digital Tech

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A self-timed microarchitecture called KeyRing is presented, and a method for implementing KeyRing circuits compatible with a timing-driven electronic design automation (EDA) flow is discussed. The KeyRing microarchitecture is derived from the AnARM, a low-power self-timed ARM processor based on ad hoc design principles. First, the unorthodox design style and circuit structures are revisited. A theoretical model that can support the design of generic circuits and the elaboration of EDA methods is then presented. Also addressed are the compatibility issues between KeyRing circuits and timing-driven EDA flows. The proposed method leverages relative timing constraints to translate the timing relations in a KeyRing circuit into a set of timing constraints that enable timing-driven synthesis and static timing analysis. Finally, two 32-bit RISC-V processors are presented; called KeyV and based on KeyRing microarchitectures, they are synthesized in a 65 nm technology using the proposed EDA flow. Postsynthesis results demonstrate the effectiveness of the design methodology and allow comparisons with a synchronous alternative called SynV. Performance and power consumption evaluations show that KeyV has a power efficiency that lies between SynV with clock-gating and SynV without clock-gating.

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Optimization of Small-Delay Defects Test Quality by Clock Speed Selection and Proper Masking Based on the Weighted Slack Percentage

Cited by 9 publications

References 35 publications

FATE: A Flexible FPGA-Based Automatic Test Equipment for Digital ICs

FATE: A Flexible FPGA-Based Automatic Test Equipment for Digital ICs

Optimal Test Clock Frequency Based Test Option Generation for Small Delay Defects

Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow

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