Optimization of sub-5-nm multiple-thickness gate oxide formed by oxygen implantation

King, Ya‐Chin; Kuo, C.; King, Tsu‐Jae; Hu, Chenming

doi:10.1109/16.925262

Cited by 6 publications

(3 citation statements)

References 9 publications

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“…Low-pressure CVD is the most common, but different underlayers, such as SiO 2 , HF-treated SiO 2 [44], Si 3 N 4 [81], oxynitride [82] and Al 2 O 3 [83], have been examined. Others include remote-plasma-enhanced CVD [84], aerosol fabrication [85], annealing of silicon-rich oxide [86], ion implantation of Si, Ge or Sn into SiO 2 followed by annealing [87,88] and Ge implant into Si followed by oxidation [89].…”

Section: Multi-dot Memories With Mosfetmentioning

confidence: 99%

Silicon single-electron devices

Takahashi

Ono

Fujiwara

et al. 2002

J. Phys.: Condens. Matter

131

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Single-electron devices (SEDs) are attracting a lot of attention because of their capability of manipulating just one electron. For their operation, they utilize the Coulomb blockade (CB), which occurs in tiny structures made from conductive material due to the electrostatic interactions of confined electrons. Metals or III–V compound semiconductors have so far been used to investigate the CB and related phenomena from the physical point of view. However, silicon is preferable from the viewpoint of applications to integrated circuits because, on a silicon substrate, SEDs can be used in combination with conventional complementary metal-oxide-semiconductor (CMOS) circuits. In addition, the well established fabrication technologies for CMOS large-scale integrated circuits (LSIs) can be applied to making such small structures. LSI applications of the silicon SEDs can be categorized into two fields: memory and logic. Many kinds of device structure and fabrication process have been proposed and tested for these purposes. This paper introduces the current status of silicon-based SED studies for LSI applications.

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Section: Multi-dot Memories With Mosfetmentioning

confidence: 99%

Silicon single-electron devices

Takahashi

Ono

Fujiwara

et al. 2002

J. Phys.: Condens. Matter

131

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“…Whereas research on nc memories has mainly focused on Si-nc, Ge is also of interest because of its smaller band-gap, inducing better theoretical retention and faster writing/erasing times [5,6]. As previously demonstrated by Klimlenkov et al [7], Ge (unlike Si) does not follow the implantation profile after thermal annealing.…”

Section: Introductionmentioning

confidence: 99%

Retention in metal–oxide–semiconductor structures with two embedded self-aligned Ge-nanocrystal layers

Duguay

Burignat

Kern

et al. 2007

Semicond. Sci. Technol.

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Structural and electrical characterization has been carried out on metal-oxide-semiconductor (MOS) structures with a silicon dioxide (SiO 2 ) layer containing a germanium nanocrystals (Ge-ncs) floating gate. Ge-nc layers were embedded in SiO 2 by ion implantation with subsequent annealing. Structural analysis proved the presence of two self-aligned nanocrystal layers within the SiO 2 host material. The electrical results indicate a strong memory effect due to the presence of a near-interface Ge-nc layer. Few volts memory windows can easily be obtained at relatively low programming voltages (<6 V). For comparison, operating voltages used in current FLASH technology are about 12 V. Despite its promising structural properties, retention times extracted from capacitance measurements and scanning Kelvin microscopy were found to be too low (∼10 5 s) to comply with the non-volatility industry requirements (<10 years required).

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“…Togo et al [2] demonstrated system-on-a-chip fabrication for dual gate CMOS field-effect transistors (FETs) with multiple-thickness gate oxides by using Ar + and N + implantation. King et al [3] have demonstrated the method of using masked oxygen implantation. The use of both Ar + and N + implantation produces a 20% difference in gate oxide thickness between the low-speed memory device region and the high-performance logic region.…”

Section: Introductionmentioning

confidence: 99%

Multiple gate oxide technology using nitrogen implantation and high-pressure O₂oxidation

Lee

Kwong

2002

Semicond. Sci. Technol.

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We demonstrate a novel process for multiple gate oxide technology using a combination of nitrogen implantation and high-pressure O 2 oxidation. Using this approach we realize a range of different thicknesses from 26 to 140 Å simultaneously on a silicon wafer. A secondary ion mass spectroscopy profile shows an identical nitrogen peak that cannot be obtained by conventional oxynitridation. A vertical high-pressure (VHP) O 2 device shows a leakage current about ten times lower and only ∼40 mV difference in V FB compared to the SiO 2 device when the nitrogen dose is 7 × 10 14 atoms cm −2 . The elimination of boron penetration is observed after a drive-in of 1050 • C for 30 s. In this work, we demonstrate a novel approach to realize >500% difference in the oxide growth rate using VHP oxidation (15-25 atm at 750-850 • C) and N implantation (between 1 × 10 14 and 3 × 10 15 atoms cm −2 ).

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Optimization of sub-5-nm multiple-thickness gate oxide formed by oxygen implantation

Cited by 6 publications

References 9 publications

Silicon single-electron devices

Silicon single-electron devices

Retention in metal–oxide–semiconductor structures with two embedded self-aligned Ge-nanocrystal layers

Multiple gate oxide technology using nitrogen implantation and high-pressure O₂oxidation

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Optimization of sub-5-nm multiple-thickness gate oxide formed by oxygen implantation

Cited by 6 publications

References 9 publications

Silicon single-electron devices

Silicon single-electron devices

Retention in metal–oxide–semiconductor structures with two embedded self-aligned Ge-nanocrystal layers

Multiple gate oxide technology using nitrogen implantation and high-pressure O2oxidation

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Multiple gate oxide technology using nitrogen implantation and high-pressure O₂oxidation