Abstmul-Markct rleitmtids, which tequtrr! increased functionality at lurvcr costs are driving thc development of high performance CMOS tcchliologies with very high integration density. Thesc demands are pushing the coiitrnuous scaling down of techndogiEs and are ravulting In a progressive accelcration of the rate of introduction of now technology gcnerationu.Current resctirch and dcvclopmcnt activities ill CMOS technology arc focuscd on scaling the 0.25 pm CMOS technolugy generution down to 0.18 pm nr cven 0.13 pm dimcnslans. While some of the procmn modules can bc YCR~XI down in R conventional way, in some cuses scvcrc limitations are renchcd and It is ncccssary to introduce major modifications tu the process flow.In this paper we wtft present an overview of thc maiii considerations to be kept in mind when scaling down to U 0.18 pm