Optimization Simulation programming for NoC

Abstract

The article presents the concept of networks-on-chip (NoCs) as a promising alternative to communication subsystem for multiprocessor systems with bus architecture. The networks simulator developed as important software tool to estimate NoC performance parameters. The results of approbation of the developed simulator are reliance of the number of hops on the NoC dimension for mesh and torus topologies, as well as the dependences of communication links workload on the frequency, with which IP blocks generate messages. Its possibilities are considered and the accepted results are given.