Optimizations for an efficient reconfiguration of an ASIP-based turbo decoder

Abstract

International audienceThe multiplication of wireless standards is introducing the need of flexible multi-standard baseband receivers. A multi-ASIP approach for turbo decoding is an answer to reach high throughput and high flexibility. The increasing demand of throughput for new greedy application on mobile devices and the reduction of latency between two frames create the need of an efficient reconfiguration management of such multi-ASIP platforms. In this paper, we propose to tackle reconfiguration optimization of a multi-standard ASIP for turbo decoding developed during previous work. Results show that for an area overhead of 0.012 mm2 in 65 nm CMOS technology, a significant reconfiguration time optimization is achieved thanks to a reduction of the ASIP configuration load of 70%. Moreover, in a multi-ASIP context in which 8 ASIPs are implemented the configuration load is divided by ten thanks to the possibility to use a multicast mechanism for ASIP configuration loading

Advanced Hardware Design for Error Correcting Codes

“…Finally, although the chapter has mainly considered the evaluation of the architecture efficiency, similar conclusions should be driven evaluating the energy consumption and efficiency. Furthermore, several recent initiatives have proposed to tackle the aspect of reconfiguration optimization and efficient management for multi-standard ASIPbased channel decoders [49]. Finally, the promising results demonstrated in recent state-of-the-art in channel decoding have paved the way to extend this design approach to other key components of advanced communication systems.…”

“…Regarding energy optimizations the proposed architecture is an excellent candidate for a Near-Threshold circuit technique [49]. For example, the throughput of 10 Gbit/s can already be fulfilled by the presented decoder running at less than 20 MHz.…”

Dynamic configuration management of a multi-standard and multi-mode reconfigurable multi-ASIP architecture for turbo decoding

“…The RDecASIP [32,33] implements the Max-Log MAP algorithm (Sub-section 3.1) for LTE, WiMAX, and DVB-RCS standards. It supports both single and double binary convolutional turbo codes and implements radix-4 trellis compression technique for SBTC mode.…”

“…Thus, at run-time, all these parameters need to be computed and loaded into the configuration memories when a new configuration is required. For optimizing the configuration latency, the configuration memory has been organized in a way that allows broacasting and multi-casting transfers [32,33]. In this context, the configuration latency of the UDec platform using the proposed configuration infrastructure is defined by (11) [31].…”

“…On the other side, it should be divided by the number of ASIPs per component decoder (N ASIP /2). Finally, 10 clock cycles should be added once due to the 10 pipeline stages of the ASIP [32,33].…”