Optimized Circuit Failure Prediction for Aging: Practicality and Promise

Agarwal, M.; Balakrishnan, Varsha; Bhuyan, Anshuman; Kim, Kyunglok; Paul, B.C.; Wang, Wenping; Yang, Bo; Cao, Yu; Mitra, Subhasish

doi:10.1109/test.2008.4700619

Cited by 120 publications

(109 citation statements)

References 12 publications

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“…Therefore, a safe and tight upper bound for circuit delay degradation under worst-case signal probabilities is required for reliable operation. In most practical cases, it can be obtained by assuming WC-K aging of 0.95 for the entire circuit [5], [21], [22], [38]. Worst-case aging during time-step i implies that the system is always in the active mode under worst-case workload, i.e., η (i) = 1 and K aging(i) = WC-K aging .…”

Section: E Threshold Voltagementioning

confidence: 99%

“…The specific degraded delay depends on input vectors during operation, which are not known ahead of time. A worst-case scenario is considered to guarantee reliable operation [21], [22], [38]. As seen in (17), delay decreases at lower temperatures.…”

Section: H Delaymentioning

confidence: 99%

“…Simulation results in Section IV take those non-idealities into account, derive design guidelines to maximize PRTA benefits, and demonstrate that PRTA is highly beneficial for systems that experience workload with low stress probability characteristics. Real-time aging information for PRTA can be obtained (or calibrated) from a variety of sources: 1) on-chip ring oscillators or other canary equivalent circuits [27]- [32]; 2) on-chip sensors such as temperature sensors (by predicting aging based on temperature profiles and assuming worst-case workload profiles) [33]- [36]; 3) delay shift detectors [11], [21], [37]; 4) on-line self-test and self-diagnostics [38]- [40]; and 5) indirectly measuring degradation by adjusting selftuning parameters until failure occurs.…”

Section: Progressive-real-time-aging-assisted (Prta)mentioning

confidence: 99%

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Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Mintarno

Skaf

Zheng

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper presents an integrated framework, together with control policies, for optimizing dynamic control of self-tuning parameters of a digital system over its lifetime in the presence of circuit aging. A variety of self-tuning parameters such as supply voltage, operating clock frequency, and dynamic cooling are considered, and jointly optimized using efficient algorithms described in this paper. Our optimized self-tuning approach satisfies performance constraints at all times, and maximizes a lifetime computational power efficiency (LCPE) metric, which is defined as the total number of clock cycles achieved over lifetime divided by the total energy consumed over lifetime. We present three control policies: 1) progressive-worst-case-aging (PWCA), which assumes worst-case aging at all times; 2) progressive-on-stateaging (POSA), which estimates aging by tracking active/sleep modes, and then assumes worst-case aging in active mode and long recovery effects in sleep mode; and 3) progressive-real-timeaging-assisted (PRTA), which acquires real-time information and initiates optimized control actions. Various flavors of these control policies for systems with dynamic voltage and frequency scaling (DVFS) are also analyzed. Simulation results on benchmark circuits, using aging models validated by 45 nm measurements, demonstrate the effectiveness and practicality of our approach in significantly improving LCPE and/or lifetime compared to traditional one-time worst-case guardbanding. We also derive system design guidelines to maximize self-tuning benefits.Index Terms-Adaptive supply voltage and clock frequency, circuit aging, energy-efficiency, lifetime reliability.

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Section: E Threshold Voltagementioning

confidence: 99%

Section: H Delaymentioning

confidence: 99%

Section: Progressive-real-time-aging-assisted (Prta)mentioning

confidence: 99%

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Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Mintarno

Skaf

Zheng

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…These exploit timing error detection and correction mechanisms to overcome increased timing error rates. In addition, transistor aging problems significantly impact the performance of nanometer circuits resulting in the appearance of timing errors during their normal lifetime [4][5]. Such an example is the Negative Bias Temperature Instability (NBTI) induced aging of PMOS transistors which degrades their threshold voltage over time increasing path delays.…”

Section: Cmos Nanotechnologies and Timing Errorsmentioning

confidence: 99%

Timing Error Detection and Correction by Time Dilation

Floros

Tsiatouhas

Kavousianos

2010

IFIP Advances in Information and Communication Technology

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Abstract. Timing failures in high complexity -high frequency integrated circuits, which are mainly caused by test escapes and environmental as well as operating conditions, are a real concern in nanometer technologies. The Time Dilation design technique supports both on-line (concurrent) error detection/correction and off-line scan testing. It is based on a new scan Flip-Flop and provides multiple error detection and correction at the minimum penalty of one clock cycle delay at the normal circuit operation for each error correction. No extra memory elements are required, like in earlier design approaches in the open literature, reducing drastically the silicon area overhead, while the performance degradation is negligible since no extra circuitry is inserted in the critical paths of a design.

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“…While such a method is guaranteed to be pessimistic, the pessimism may be too large. Some works have attempted to overcome this by using a worst-case stress probability of 0.95 instead of 1.0 on each gate [10], but this is purely empirical. Precise aging information is only obtainable from expensive postsilicon aging measurements performed directly on the circuit [12]- [14] instead of using surrogate sensors.…”

Section: Introductionmentioning

confidence: 99%

ReSCALE: Recalibrating sensor circuits for aging and lifetime estimation under BTI

Sengupta¹,

Sapatnekar²

2014

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Abstract-Bias temperature instability (BTI) induced delay shifts in a circuit depend strongly on its operating environment. While sensors can capture some operating parameters, they are ineffective in measuring vital performance shifts due to changes in the workloads and signal probabilities. This paper determines the delay of an aged circuit by amalgamating more frequent measurements on ringoscillator sensors with infrequent online delay measurements on a monitored circuit to recalibrate the sensors. Our approach reduces the pessimism in predicting circuit delays, thus permitting lower delay guardbanding overheads compared to conventional methods.

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Optimized Circuit Failure Prediction for Aging: Practicality and Promise

Cited by 120 publications

References 12 publications

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Timing Error Detection and Correction by Time Dilation

ReSCALE: Recalibrating sensor circuits for aging and lifetime estimation under BTI

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