Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology

Abstract

Inter-processor communication and synchronization are critical problems in embedded multiprocessors. In order to achieve high-speed communication and low-latency synchronization, most recent designs employ dedicated hardware engines to support these communication protocols individually, which is complex, inflexible, and error prone. Thus, this paper motivates the optimization of inter-processor communication and synchronization by using application-specific instruction-set processor (ASIP) techniques. The proposed communication mechanism is based on a set of custom instructions coupled with a low-latency on-chip network, which provides efficient support for both data transfer and process synchronization. By using state-of-the-art ASIP design methodology, we embed the communication functionalities into a base processor, making the proposed mechanism feature ultra low overhead. More importantly, industry-standard compatible programming interfaces supporting both message-passing and shared-memory paradigms are exposed to end-users to ease the software porting. Experimental results show that the bandwidth of the proposed message-passing protocol can achieve up to 703 Mbyte/s @ 200 MHz, and the latency of the proposed synchronization protocol can be reduced by more than 81% when compared with the conventional approach. Moreover, as a case study, we also show the effectiveness of the proposed communication mechanism in a real-life embedded application, WiMedia UWB MAC.

Distributed Synchronization for Message-Passing Based Embedded Multiprocessors

“…For comparison, we also implement three other synchronization models, one is the conventional polling model and the other two are centralized contention-free models for shared-memory (hereinafter, "SM") [5] and messagepassing (hereinafter, "MP") [6] architectures, respectively. First, to evaluate the performance of the lock, we use two micro-benchmarks introduced in [9].…”

“…We implement the proposed synchronization model in our hybrid shared-memory/message-passing MPSoC architecture [6]. As shown in Fig.…”

“…The proposed synchronization model is programmed according to our ASIP programming model [6]. A custom instruction, msg send, is used to implement the synchronization request, which issues a single-word (32 bit) message to a specified base processor.…”

“…In order to address these problems, a hardware-supported solution is proposed in [4], where a centralized hardware engine monitors all synchronization requests globally and serves them in a first-in-firstout (FIFO) order. In our previous work [5], [6], two centralized hardware engines are proposed to support the synchronization for shared-memory and message-passing MPSoC architectures, respectively. Our recent work [7] further optimizes the centralized controller in [6] by enabling it to support fully queued lock synchronization.…”

“…In our previous work [5], [6], two centralized hardware engines are proposed to support the synchronization for shared-memory and message-passing MPSoC architectures, respectively. Our recent work [7] further optimizes the centralized controller in [6] by enabling it to support fully queued lock synchronization. However, these centralized solutions fundamentally introduce a bottleneck when the system scales to more cores.…”