Optimized Design Methodology for an Integration of Electrical Control Systems

Kebbati, Youssef; Souffi, Hayet

doi:10.1109/ccece.2007.414

Cited by 1 publication

(1 citation statement)

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“…The authors of Reference [44] describe how agile methodologies can be applied to hardware design by splitting work packets into small tasks, and in Reference [72] a methodology around software hardware partitioning based on the manual evaluation of design guidelines is presented. In Reference [35], the authors describe a methodology for the design of electrical control systems that tries to split complex algorithms into smaller modules to ease implementation and improve reusability. The contributions in Reference [57] provide a great overview on the ways in which SystemC can be used to accurately model an algorithm in the context of hardware design.…”

Section: Related Workmentioning

confidence: 99%

On Predictable Reconfigurable System Design

Voss

Kwaadgras

Mencer

et al. 2021

ACM Trans. Archit. Code Optim.

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We propose a design methodology to facilitate rigorous development of complex applications targeting reconfigurable hardware. Our methodology relies on analytical estimation of system performance and area utilisation for a given specific application and a particular system instance consisting of a controlflow machine working in conjunction with one or more reconfigurable dataflow accelerators. The targeted application is carefully analyzed, and the parts identified for hardware acceleration are reimplemented as a set of representative software models. Next, with the results of the application analysis, a suitable system architecture is devised and its performance is evaluated to determine bottlenecks, allowing predictable design. The architecture is iteratively refined, until the final version satisfying the specification requirements in terms of performance and required hardware area is obtained. We validate the presented methodology using a widely accepted convolutional neural network (VGG-16) and an important HPC application (BQCD). In both cases, our methodology relieved and alleviated all system bottlenecks before the hardware implementation was started. As a result the architectures were implemented first time right, achieving state-of-the-art performance within 15% of our modelling estimations.

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Section: Related Workmentioning

confidence: 99%