Optimized Hardware Implementation of Vedic Binary Multiplier using Nikhilam Sutra on FPGA

Modified Architecture for Nikhilam Navatshcaramam Dashath (NND) Vedic Multiplier

“…The proposed 4 and 8 bit multipliers are 26.72 % and 16.16% delay efficient as compared to reported architecture (1) respectively. With the implementation on Artix-7 the proposed design of 4 bit multiplier is 28.43% efficient in comparison with (1) and 78.7% efficient than (11) .…”

“…This resulted an improvement in performance parameters. When implemented on Vertex-7, the proposed 4 and 8 bit multipliers are 26.72 % and 16.16% delay efficient as compared to reported architecture (1) respectively. The proposed 17 bit NND multiplier is 58.3%, 73.3 % area and 71.77%, 39.39% delay efficient as compared to array and Vedic UT multipliers respectively.…”

“…The proposed architecture is efficient in terms of area, delay and power as compared to the array and Vedic Urdhva Tiryakbyham (UT) multiplier. The 4 bit NND multiplier is 26.72 % delay and 47.05 % area efficient as compared to the reported architecture (1) . To compare with other reported architecture, the results are also taken on Artix-7, Device: XC7A100T Package: CSG324, and Spartan-6, Device: XC6SLX4 Package: TQG144 FPGA.…”

“…Palak Yesh et. al (1) have proposed the architecture of NND multiplier. This architecture uses the two's complement, multiplier, binary adder and subtractor and left shifter blocks.…”