Optimized leakage control in CMOS NAND gates: the in-triggering technique

Abstract

Leakage power, now the largest contributor to integrated circuit power consumption, is rising quickly, according to the International Technology Roadmap for Semiconductors (ITRS). As CMOS (complementary metal-oxide semiconductor) technology continues to shrink to deep submicron levels, gate leakage and subthreshold have become important components that contribute to total power dissipation. To address this problem, many methods have been put forth, especially at the circuit level. In 45 nm CMOS, variability and short-channel effects limit noise margins and compromise gate delays, thereby compromising the timing closure and robustness of ultra-low voltage circuits. The resulting supply voltage guardband may reduce energy efficiency in order to achieve a reasonable production yield. Furthermore, the high leakage currents of these technologies decrease energy efficiency when idle intervals are prolonged. In this study, two designs of a novel two-input NAND gate at 45 nm CMOS technology are constructed using eight transistors (8-T). A novel circuit technique named "In-Triggering (INDEP with Bi-Triggering)" is presented in this study with the goal of lowering subthreshold leakage in digital circuits. This method is thoroughly contrasted with other leakage reduction strategies now in use, such as Base, Sleepy LECTOR, LECTOR, INDEP, and Bi-Triggering procedures. Evaluation is done using key performance measures such power-delay product (PDP), latency, subthreshold leakage power, and total power consumption. 45-nm Predictive Technology Models (PTM) with a nominal supply voltage of 1V are used in the investigation. According to our findings, the suggested In-Triggering technique outperforms the conventional NAND gate in terms of speed by 12% and significantly reduces leakage power by up to 56%. Furthermore, compared to the Base, Trig01, and INDEP NAND gates, the method offers mean power savings of 58.8%, 36.1%, and 30.7%, respectively. At supply voltages of 1V, a comprehensive comparison and verification are then conducted utilizing the several proposed and existing methodologies. The effectiveness of the In-Triggering technique in reducing leakage power in CMOS circuits is confirmed by comparing these results to the most well-known design strategies for both active operation and sleep modes.