Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation

Abstract

Power consumption and speed are the main criteria in designing comparator for analog-to-digital converter (ADC). This paper presents an optimized low voltage low power dynamic comparator which is robust to process, voltage and temperature (PVT) variations with adequate speed. The comparator circuit was designed using 0.18µm CMOS technology with low voltage supply of 0.8V. The method used to verify the robustness of the comparator circuit across 45 PVT is presented. The circuit is simulated with 10% voltage supply variation, five process corners and temperature variation from 0°C to 100°C. The simulation result show that the proposed comparator circuit achieved significant reduction of power consumption and delay during worst case condition compared to dynamic comparator proposed from previous researchers.

A low power and high speed 45 nm CMOS dynamic comparator with low offset

“…In the pre-amplifier of a two-stage comparator [29], a pMOS latch and crosscoupled circuit are used to enhance speed, but at the expense of offset and power consumption. Recent advancements in dynamic comparators [30]- [35] include techniques such as cross-coupled transistors in the latching stage [30], which enhance transconductance but introduce significant offset voltage, affecting accuracy. Additionally at high operating frequencies the comparator operates at low speed and consumes high power and causes high offset.…”