Optimized rapid prototyping for real-time embedded heterogeneous multiprocessors

Grandpierre, Thierry; Lavarenne, C.; Sorel, Yves

doi:10.1109/hsc.1999.777396

Cited by 45 publications

(37 citation statements)

References 15 publications

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“…8 When the number of available nodes is higher (19)(20)(21)(22)(23)(24)(25)(26)(27)(28)(29)(30)(31)(32), no further parallelism can be exploited and hence efficiency decreases. When the number is smaller (4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18), the kernel sequentialises some processings on some nodes (thus providing a form of "virtualisation" mechanism).…”

Section: Resultsmentioning

confidence: 99%

“…SKiPPER-I relied on a mostly static execution model for skeletons: most of the decisions regarding distribution of computations and scheduling of communications were made at compile time by a third-party CAD software called Syn-DEx [14]. This implementation path, while resulting in very efficient distributed executives for "static"-by static we mean that the distribution and scheduling of all communications do not depend on input data and can be predicted at compile-time-did not directly support "dynamic" skeletons, in particular those based on data or task farming (DF and TF).…”

Section: Skipper-iimentioning

confidence: 99%

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Managing Algorithmic Skeleton Nesting Requirements in Realistic Image Processing Applications: The Case of the SKiPPER-II Parallel Programming Environment's Operating Model

Coudarcher

Duculty

Sérot

et al. 2005

EURASIP J. Adv. Signal Process.

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SKiPPER is a SKeleton-based Parallel Programming EnviRonment being developed since 1996 and running at LASMEA Laboratory, the Blaise-Pascal University, France. The main goal of the project was to demonstrate the applicability of skeleton-based parallel programming techniques to the fast prototyping of reactive vision applications. This paper deals with the special features embedded in the latest version of the project: algorithmic skeleton nesting capabilities and a fully dynamic operating model. Throughout the case study of a complete and realistic image processing application, in which we have pointed out the requirement for skeleton nesting, we are presenting the operating model of this feature. The work described here is one of the few reported experiments showing the application of skeleton nesting facilities for the parallelisation of a realistic application, especially in the area of image processing. The image processing application we have chosen is a 3D face-tracking algorithm from appearance.

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Section: Resultsmentioning

confidence: 99%

Section: Skipper-iimentioning

confidence: 99%

Managing Algorithmic Skeleton Nesting Requirements in Realistic Image Processing Applications: The Case of the SKiPPER-II Parallel Programming Environment's Operating Model

Coudarcher

Duculty

Sérot

et al. 2005

EURASIP J. Adv. Signal Process.

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show abstract

“…The Prelude language [20], belongs to the Synchronous Languages family. Compilation of synchronous languages for distributed hardware platforms was studied in [4,12,13], but with a single execution thread per CPU. Compilation into multi-thread/multi-task code was proposed for Prelude in [20], then for control-flow synchronous languages in [33,34] and for Scade in [19].…”

Section: Related Workmentioning

confidence: 99%

Code generation for multi-phase tasks on a multi-core distributed memory platform

Fort¹,

Forget²

2019

2019 IEEE 25th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

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To cite this version:Frédéric Fort, Julien Forget. Code generation for multi-phase tasks on a multi-core distributed memory platform. AbstractEnsuring temporal predictability of real-time systems on a multi-core platform is difficult, mainly due to hard to predict delays related to shared access to the main memory. Task models where computation phases and communication phases are separated (such as the PRedictable Execution Model [23]), have been proposed to both mitigate these delays and make them easier to analyze.In this paper we present a compilation process, part of the Prelude compiler [20], that automatically translates a high-level synchronous dataflow system specification into a PREM-compliant C program. By automating the production of the PREM-compliant C code, low-level implementation concerns related to task communications become the responsibility of the compiler, which saves tedious and error-prone development efforts.

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“…Greedy list heuristics are used in the context of offline multi-core scheduling since they are very fast. In the following, we propose a greedy list heuristic inspired by [11] for scheduling operation graphs representing FMU cosimulations under real-time constraints. The proposed heuristic is priority based.…”

Section: Multi-core Scheduling Heuristicmentioning

confidence: 99%

Scheduling Real-Time HiL Co-Simulation of Cyber-Physical Systems on Multi-Core Architectures

Saidi

Pernet

Sorel

2018

2018 IEEE 24th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

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When designing complex cyber-physical systems, engineers have to integrate numerical models from different modeling environments in order to simulate the whole system and estimate its global performances. Co-simulation refers to such joint simulation of heterogeneous models. If some parts of the system are physically available, it is possible to connect these parts to the co-simulation in a Hardware-in-the-Loop (HiL) approach. In this case, the simulation has to be performed in realtime where models execution consists in periodically reacting to the real (physically available) components and providing periodic output updates. This paper deals with the parallelization and scheduling of real-time Hardware-in-the-Loop co-simulation of numerical models on multi-core architectures. A method for defining real-time constraints that have to be met is proposed. Also, an ILP formulation as well as a heuristic are proposed to solve the problem of scheduling the co-simulation on a multicore architecture while satisfying the previously defined real-time constraints. The proposed approach is evaluated for different sizes of co-simulations and multi-core processors.

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Optimized rapid prototyping for real-time embedded heterogeneous multiprocessors

Cited by 45 publications

References 15 publications

Managing Algorithmic Skeleton Nesting Requirements in Realistic Image Processing Applications: The Case of the SKiPPER-II Parallel Programming Environment's Operating Model

Managing Algorithmic Skeleton Nesting Requirements in Realistic Image Processing Applications: The Case of the SKiPPER-II Parallel Programming Environment's Operating Model

Code generation for multi-phase tasks on a multi-core distributed memory platform

Scheduling Real-Time HiL Co-Simulation of Cyber-Physical Systems on Multi-Core Architectures

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