Optimized self-tuning for circuit aging

Mintarno, Evelyn; Skaf, Joëlle; Zheng, Rui; Velamala, Jyothi; Cao, Yu; Boyd, Stephen; Dutton, R.W.; Mitra, Subhasish

doi:10.1109/date.2010.5457140

Cited by 22 publications

(5 citation statements)

References 36 publications

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“…INTRODUCTION Thereafter, the circuit is fine-tuned with either adaptive body biasing, and supply voltage or dynamic frequency scaling. Mintarno et al investigated in [161,162] a scheme for dynamic control optimization of different self-adjusting parameters such as dynamic cooling, supply voltage, and clock frequency over lifetime for the circuit aging. Oboril et al presented in [163] a dynamic run-time approach using voltage and frequency scaling which depend on run-time monitoring of temperature, performance, power and aging.…”

Section: Dynamic Adaptation Techniquesmentioning

confidence: 99%

Reliability Modeling and Mitigation for Embedded Memories

Agbo

Taouil

Hamdioui

2019

2019 IEEE International Test Conference (ITC)

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Complementary Metallic Oxide Semiconductor (CMOS) technology scaling enhances the performance, transistor density, functionality, and reduces cost and power consumption. However, scaling causes significant reliability challenges both from a manufacturing and operational point of view. Obtaining reliable memories require accurate understanding of the impact of aging (such as Bias temperature instability (BTI)) on individual memory components and how they interact with each other. In this dissertation, two types of challenges are addressed, which are related to BTI aging and partially to mitigation schemes: one related to the aging of sense amplifier and another one to the aging of read path and write path. Analysis of aging impact on different memory sense amplifiers-The analysis of BTI impact on various memory sense amplifier (SA) designs was performed, while taking into account two BTI models (i.e., Atomistic and RD model), different technology nodes (i.e., 90, 65, 45, 32, 22, and 16 nm), and different workloads. First, the analysis and comparison of RD and Atomistic models impact on the SA were performed. The results show that the atomistic trap-based BTI model is more accurate than the RD model. Second, the investigation of BTI impact on the drain-input latch type SA for various technology nodes and supply voltages was performed. The result shows that as technology scales down, the impact of BTI on sensing delay increases, while the sensing voltage decreases, causing less robust and reliable memory sense amplifier. The result also shows that increase in supply voltage compensates the BTI degradation. Third, an accurate technique was proposed and characterized for the integral impact of BTI and voltage temperature variation on the memory standard latch type SA for various technology nodes and workloads. The results show that the degradation is strongly dependent on workload and temperature. Fourth, in addition to the latter, the impact of process variation at timezero was incorporated and analyzed. The results show that the SA sensing delay degradation is more significant at lower nodes and could lead to read failures at lower power supply. This reveals that there must be a tradeoff between performance and reliability. Fifth, an accurate methodology was proposed to quantify the impact of variability on the memory SA offset-voltage for both time-zero and time-dependent variability. The results show that the impact on the offset voltage specification is significant for aging time-dependent variability. Sixth, on top of the latter, the sensitivity of the SA and its failure rate were analyzed for five process corners (i.e., Nominal, Fast-Fast, Fast-Slow, Slow-Fast, and Slow-Slow). The results show that balanced workloads result in a significant low offset voltage specification. Finally, the impact of aging was analyzed and compared, while considering different supply voltages, temperatures, and SA designs. The results show that the High Performance SA degrades faster than other SA types, irrespective of the workloa...

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Section: Dynamic Adaptation Techniquesmentioning

confidence: 99%

Reliability Modeling and Mitigation for Embedded Memories

Agbo

Taouil

Hamdioui

2019

2019 IEEE International Test Conference (ITC)

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“…One-time worst-case guardbanding at design stage such as gate sizing is either inadequate or otherwise over-pessimistic that leaves a lot of performance on the table [2], as circuit can age at different rates depending on several factors, especially workload that is unknown at design stage. Thus, it is necessary to monitor the aging on the chip and react dynamically.…”

Section: Introductionmentioning

confidence: 99%

Representative critical reliability paths for low-cost and accurate on-chip aging evaluation

Wang¹,

Chen²,

Tehranipoor³

2012

Proceedings of the International Conference on Computer-Aided Design

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Aging of transistors degrades circuit performance and can potentially lead to functional failure in the field. This has become a major reliability concern especially when technology further scales to 45 nm and below. It is thus necessary to design on-chip structures that can provide accurate aging evaluation with no performance penalty. In this paper, we propose a novel methodology to accurately evaluate aging in the field. Representative Critical Reliability Paths (RCRPs) are synthesized as a stand-alone circuit to represent the aging of critical reliability paths, which are defined as paths that can potentially become critical at some point in time due to aging. By monitoring the RCRPs, aging of the critical reliability paths can be efficiently and accurately evaluated with no impact on the normal operation of the chip. The aging evaluation results can then be exploited to guide on-chip performance calibration to ensure lifetime reliability. Simulation results demonstrate the efficiency of the proposed structure.

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“…the amount of stress caused by the currently running application. Degradation rate monitoring is crucial for the timely adoption of preventive techniques that alleviate aging, such as proactive frequency and voltage scaling [4] or dynamic cooling [5].…”

Section: Introductionmentioning

confidence: 99%

On-Line Prediction of NBTI-induced Aging Rates

Baranowski¹,

Firouzi²,

Kiamehr³

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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Nanoscale technologies are increasingly susceptible to aging processes such as Negative-Bias Temperature Instability (NBTI) which undermine the reliability of VLSI systems. Existing monitoring techniques can detect the violation of safety margins and hence make the prediction of an imminent failure possible. However, since such techniques can only detect measurable degradation effects which appear after a relatively long period of system operation, they are not well suited to early aging prediction and proactive aging alleviation. This work presents a novel method for the monitoring of NBTI-induced degradation rate in digital circuits. It enables the timely adoption of proper mitigation techniques that reduce the impact of aging. The developed method employs machine learning techniques to find a small set of so called Representative Critical Gates (RCG), the workload of which is correlated with the degradation of the entire circuit. The workload of RCGs is observed in hardware using so called workload monitors. The output of the workload monitors is evaluated on-line to predict system degradation experienced within a configurable (short) period of time, e.g. a fraction of a second. Experimental results show that the developed monitors predict the degradation rate with an average error of only 1.6% at 4.2% area overhead.

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Optimized self-tuning for circuit aging

Cited by 22 publications

References 36 publications

Reliability Modeling and Mitigation for Embedded Memories

Reliability Modeling and Mitigation for Embedded Memories

Representative critical reliability paths for low-cost and accurate on-chip aging evaluation

On-Line Prediction of NBTI-induced Aging Rates

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