Optimized Sequence Dataset Generation for a Two-Stage Pipelined Microcontroller Instruction-Level Electromagnetic Information Leakage Analysis

Abstract

With the prevalence of the Internet of Things (IoT) and microcontrollers (MCUs), the security issues of IoT and MCUs have become increasingly important. Side-channel analysis (SCA) is a major threat to such problems. One of the non-invasive SCAs is through electromagnetic information leakage (EM-leak) analysis. The author has developed a machine-instruction-level EM-leak analysis by neural network (NN) model. The NN model analysis need a large dataset for training and validation. And the dataset should be complete and sufficient. The dataset sufficiency can be achieved by acquiring more data from the already proposed EM-leak measurement platform. However, the completeness issue becomes a challenge due to the pipelined architecture in the target MCU. In this paper, the completeness issue of a NN model dataset for the EM-leak analysis is addressed. The issue is to be solved in several steps. First, it is simplified to a two-stage pipelined MCU individual EM-leak analysis sequence problem (2-EMAseq). The problem is then proved that at least one optimal solution exists. And an algorithm is proposed based on the proof to find an optimal solution (a complete EM-leak NN dataset). Experiments show that the proposed algorithm can find an optimal solution. The contributions of this paper include: it successfully reduces a real problem to a 2-EMAseq description, proves that the 2-EMAseq problem has at least one optimal solution, uses this proof to develop an algorithm, and uses this algorithm to find a complete dataset is the target two-stage pipelined MCU dataset for NN model training/validation. Currently, the algorithm can only generate the optimal EM-dataset for twostage pipelined MCUs. However, there are many MCUs with 4~8 pipeline stages. Whether there is an optimal solution when the stages are more than two is still an open question. And it needs to find proofs or derive heuristics in the future for such MCUs.