Optimizing an Analog Neuron Circuit Design for Nonlinear Function Approximation

Neckar, Alexander; Stewart, Terrence C.; Benjamin, Ben Varkey; Boahen, Kwabena

doi:10.1109/iscas.2018.8351459

Cited by 6 publications

(4 citation statements)

References 14 publications

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“…For instance, a sensory neuron that is orientation-selective selectively response to different orientations (encoding), and the information conveyed by this neuron is a measure of the extent to which a given input is correctly estimated from the paired output (decoding), which is evaluated by H(In|Out) in Eq. (6).…”

Section: Neural Coding Schemesmentioning

confidence: 99%

Tutorial: Neuromorphic spiking neural networks for temporal learning

Jeong

2018

Journal of Applied Physics

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Spiking neural networks (SNN) as time-dependent hypotheses consisting of spiking nodes (neurons) and directed edges (synapses) are believed to offer unique solutions to reward prediction tasks and the related feedback that are classified as reinforcement learning. Generally, temporal difference (TD) learning renders it possible to optimize a model network to predict the delayed reward in an ad hoc manner. Neuromorphic SNNs-networks built using dedicated hardware-particularly leverage such TD learning for not only reward prediction but also temporal sequence prediction in a physical time domain. In this tutorial, such learning in a physical time domain is referred to as temporal learning to distinguish it from conventional TD learning-based methods that generally involve algorithmic (rather than physical) time. This tutorial addresses neuromorphic SNNs for temporal learning from the scratch. It first concerns general characteristics of SNNs including spiking neurons and information coding schemes and then moves on to temporal learning including its general concept, feasible algorithms, and their association with neurophysiological learning rules that have intensively been enriched for the last few decades.Most of neuromorphic systems built using analog building blocks are indeed based on mixed circuit. 1,3,12 The digital neuromorphic prototypes, TrueNorth 2 , SpiNNaker 4 , and Loihi 5 , highlight a fully digital circuit-based strategy in terms of flexibility of network configuration as well as neuron model parameters and learning algorithms. The progress in digital circuit fabrication techniques underpins high-speed and low-power operation of such digital neuromorphic systems. Additionally, a fieldprogrammable gate array (FPGA) is a handy and cost-effective platform for a digital neuromorphic system. To date, various architectures of spiking neurons 13,14 and neuromorphic system architecture for reconfigurable SNN 15 have been built on FPGAs.An emerging strategy is to utilize nonvolatile memory devices, e.g. oxide-based resistive memory, phase-change memory, magnetic tunnel junction, and floating-gate transistor, as synaptic devices. 16,17 Given needs for an enormous number of synapses in a neuromorphic system, replacing even in part mainstream static random access memory or content-addressable memory by such nonvolatile memories can remarkably enhance the areal density of synapses. Additionally, several nonvolatile memories represent multinary states that can further boost the areal density of synapses. 18 Such cutting edge neuromorphic hardware can leverage its capability by the aid of a user-friendly complier, for instance, equipped with graphical user interface (GUI). An example is Nengo 19 , a GUIbased compiler that readily builds an SNN on neuromorphic hardware. Lately, the complier has successfully been applied to Loihi and Braindrop.SNNs largely vary in model complexity. The complexity is generally a measure of fidelity to biological neural network. That is, the more biologically plausible, the more lik...

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Section: Neural Coding Schemesmentioning

confidence: 99%

Tutorial: Neuromorphic spiking neural networks for temporal learning

Jeong

2018

Journal of Applied Physics

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“…Many digital-or analog-implemented circuits for perceptron have been proposed in the literature, showing good results in the simulation phase [5][6][7][8], however the drawback of these works is the lack of silicon measurement results, which are of a great importance for the investigation of the fundamental characteristics of a perceptron circuit. Besides, the multi-layer perceptron (MLP) is constituted by perceptron, which is a fundamental structure for the feedforward neural network (NN), in VLSI (very-large-scale integration) implementations incorporating various learning algorithms, thus making MLP a common choice as it has been continuously researched for many years [9][10][11][12][13][14].…”

Section: Introductionmentioning

confidence: 99%

Implementation of Analog Perceptron as an Essential Element of Configurable Neural Networks

Geng

Sun

Nakatake

2020

Sensors

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Perceptron is an essential element in neural network (NN)-based machine learning, however, the effectiveness of various implementations by circuits is rarely demonstrated from chip testing. This paper presents the measured silicon results for the analog perceptron circuits fabricated in a 0.6 μm/±2.5 V complementary metal oxide semiconductor (CMOS) process, which are comprised of digital-to-analog converter (DAC)-based multipliers and phase shifters. The results from the measurement convinces us that our implementation attains the correct function and good performance. Furthermore, we propose the multi-layer perceptron (MLP) by utilizing analog perceptron where the structure and neurons as well as weights can be flexibly configured. The example given is to design a 2-3-4 MLP circuit with rectified linear unit (ReLU) activation, which consists of 2 input neurons, 3 hidden neurons, and 4 output neurons. Its experimental case shows that the simulated performance achieves a power dissipation of 200 mW, a range of working frequency from 0 to 1 MHz, and an error ratio within 12.7%. Finally, to demonstrate the feasibility and effectiveness of our analog perceptron for configuring a MLP, seven more analog-based MLPs designed with the same approach are used to analyze the simulation results with respect to various specifications, in which two cases are used to compare to their digital counterparts with the same structures.

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“…Whereas many design automation tools exist for designing digital hardware, tools for the design and modeling of special-purpose analog circuits are comparatively rare. Circuit-simulation tools have been applied to neural biomimetic [14] and prosthetics [15,16] devices and for simulating neuromorphic chips [17]. VLSI-inspired methods have been used in tools such as Cello [18] and iBioSim [19,20], but we are unaware of any existing system which transforms a highlevel biological model (a chemical reaction network) into a low-level representation for running on programmable analog hardware.…”

Section: Introductionmentioning

confidence: 99%

“…Large-scale examples of kinetic simulations also arise in genome-scale kinetic models [31,32]. Common simulation bottlenecks (Award #3835) and the Alfred P. Sloan Foundation (Award #2013- [10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29]. The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript.…”

Section: Introductionmentioning

confidence: 99%

A compiler for biological networks on silicon chips

et al. 2020

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The explosive growth in semiconductor integrated circuits was made possible in large part by design automation software. The design and/or analysis of synthetic and natural circuits in living cells could be made more scalable using the same approach. We present a compiler which converts standard representations of chemical reaction networks and circuits into hardware configurations that can be used to simulate the network on specialized cytomorphic hardware. The compiler also creates circuit-level models of the target configuration, which enhances the versatility of the compiler and enables the validation of its functionality without physical experimentation with the hardware. We show that this compiler can translate networks comprised of mass-action kinetics, classic enzyme kinetics (Michaelis-Menten, Briggs-Haldane, and Botts-Morales formalisms), and genetic repressor kinetics, thereby allowing a large class of models to be transformed into a hardware representation. Rule-based models are particularly well-suited to this approach, as we demonstrate by compiling a MAP kinase model. Development of specialized hardware and software for simulating biological networks has the potential to enable the simulation of larger kinetic models than are currently feasible or allow the parallel simulation of many smaller networks with better performance than current simulation software.

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Optimizing an Analog Neuron Circuit Design for Nonlinear Function Approximation

Cited by 6 publications

References 14 publications

Tutorial: Neuromorphic spiking neural networks for temporal learning

Tutorial: Neuromorphic spiking neural networks for temporal learning

Implementation of Analog Perceptron as an Essential Element of Configurable Neural Networks

A compiler for biological networks on silicon chips

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