2022
DOI: 10.1016/j.parco.2022.102945
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Optimizing convolutional neural networks on multi-core vector accelerator

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Cited by 5 publications
(3 citation statements)
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“…Converting the processing latency into seconds requires platform-specific assumptions regarding the required clock cycles per operation, the clock frequency, and a system's capability for parallel processing. For the remainder of this paper, a clock frequency of 1 MHz and 3 MAC operations per clock cycle were assumed [49], to provide a more intuitive comparison of the latency of the evaluated decoders. For simplicity, one addition corresponding to the sparse synaptic operation of neurons in the SNN is assumed to be equivalent to one MAC in terms of required clock cycles.…”
Section: Latencymentioning
confidence: 99%
“…Converting the processing latency into seconds requires platform-specific assumptions regarding the required clock cycles per operation, the clock frequency, and a system's capability for parallel processing. For the remainder of this paper, a clock frequency of 1 MHz and 3 MAC operations per clock cycle were assumed [49], to provide a more intuitive comparison of the latency of the evaluated decoders. For simplicity, one addition corresponding to the sparse synaptic operation of neurons in the SNN is assumed to be equivalent to one MAC in terms of required clock cycles.…”
Section: Latencymentioning
confidence: 99%
“…Converting the processing latency into seconds requires platform-specific assumptions regarding the required clock cycles per operation, the clock frequency, and a system's capability for parallel processing. For the remainder of this paper, a clock frequency of 1MHz and 3 MAC operations per clock cycle were assumed 49 . For simplicity, one addition is assumed to be equivalent to one MAC in terms of required clock cycles.…”
Section: B) the Lstm Extracts Spikes With A Temporal Resolution Of 4 ...mentioning
confidence: 99%
“…However, converting the processing latency into seconds requires platform-specific assumptions about the necessary clock cycles per operation, the clock frequency, and a system's capability to parallel process. For the rest of this paper, a clock frequency of 1MHz and 3 MAC operations per clock cycle are assumed 49 . For simplicity, one single addition is assumed to be equivalent to a MAC operation in terms of required clock cycles.…”
Section: Snnmentioning
confidence: 99%