Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS tool

Alias, Christophe; Darte, Alain; Plesco, Alexandra

doi:10.1109/asap.2010.5540967

Cited by 6 publications

(16 citation statements)

References 17 publications

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“…Memory reuse however requires additional synchronizations to avoid the worst case where all loads are performed before all tiles are executed. This is explained in more detail in Section 4, following the scheme proposed in [2], which is specific to the HLS tool C2H.…”

Section: Loop Tiling and Transformation Functionmentioning

confidence: 99%

“…We now use the theory developed in Section 3 to generate automatically a C specification of communicating processes that can be compiled into hardware by a HLS tool, namely Altera C2H, following the procedure proposed in [2]. It remains to show how the different communication and computation processes are scheduled and synchronized, in C using C2H, how the local memories (size and access function) are then defined with respect to this schedule, and how the load and store sets are finally scanned.…”

Section: Application To Hls For Fpgamentioning

confidence: 99%

“…We present the different steps of the code generation and some experimental results comparing the performances of the hardware accelerators of [2], optimized by hand, and those optimized automatically thanks to our method.…”

Section: Introductionmentioning

confidence: 99%

“…The goal of this paper is to show how the handmade restructuring demonstrated in [2] in the context of C2H, the Altera HLS tool, can be fully automated, thanks to advanced polyhedral code analysis and code generation techniques, entirely at source level (i.e., in C). We focus on the optimization of hardware accelerators that work on a large data set that cannot be completely stored in local memory, but need to be transferred from a DDR memory at the highest possible rate, and possibly temporarily stored locally.…”

Section: Introductionmentioning

confidence: 99%

“…For HLS tools to be viable, these issues need to be addressed: a) the interface should be part of the specification and/or generated by the HLS tool; b) HLS-specific optimizing program restructuring should be available, either in the tool or accessible to the designer, so that high performances (mainly throughput) can be achieved. Such high-level transformations and optimizations are standard in high-performance compilers, not yet in high-level synthesis, even if their interest has been demonstrated through hand-made designs or restructuring methodologies [19,11,6,2].…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA

Alias¹,

Darte²,

Plesco³

2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Some data-and compute-intensive applications can be accelerated by offloading portions of codes to platforms such as GPGPUs or FPGAs. However, to get high performance for these kernels, it is mandatory to restructure the application, to generate adequate communication mechanisms for the transfer of remote data, and to make good usage of the memory bandwidth. In the context of the high-level synthesis (HLS), from a C program, of hardware accelerators on FPGA, we show how to automatically generate optimized remote accesses for an accelerator communicating to an external DDR memory. Loop tiling is used to enable block communications, suitable for DDR memories. Pipelined communication processes are generated to overlap communications and computations, thereby hiding some latencies, in a way similar to double buffering. Finally, data reuse among tiles is exploited to avoid remote accesses when data are already available in the local memory.Our first contribution is to show how to generate the sets of data to be read from (resp. written to) the external memory just before (resp. after) each tile so as to reduce communications and reuse data as much as possible in the accelerator. The main difficulty arises when some data may be (re)defined in the accelerator. Our second contribution is an optimized code generation scheme, entirely at source-level, i.e., in C, that allows us to compile all the necessary glue (the communication processes) with the same HLS tool as for the computation kernel. Both contributions use advanced polyhedral techniques for program analysis and transformation. Experiments with Altera HLS tools demonstrate how to use our techniques to efficiently map C kernels to FPGA.

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Section: Loop Tiling and Transformation Functionmentioning

confidence: 99%

Section: Application To Hls For Fpgamentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA

Alias¹,

Darte²,

Plesco³

2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

Self Cite

View full text Add to dashboard Cite

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Automatic Generation of FPGA-Specific Pipelined Accelerators

Alias

Pasca

Plesco

2011

Lecture Notes in Computer Science

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Abstract-Recent increase in the complexity of the circuits has brought high-level synthesis tools as a must in the digital circuit design. However, these tools come with several limitations, and one of them is the efficient use of pipelined arithmetic operators. This paper explains how to generate efficient hardware with pipelined operators for regular codes with perfect loop nests. The part to be mapped to the operator is identified, then the program is scheduled so that each operator result is available exactly at the time it is needed by the operator, keeping the operator busy and avoiding the use of a temporary buffer. Finally, we show how to generate the VHDL code for the control unit and how to link it with specialized pipelined floating-point operators generated using open-source FloPoCo tool. The method has been implemented in the Bee research compiler and experimental results on DSP kernels show promising results with a minimum of 94% efficient utilization of the pipelined operators for a complex kernel.

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Exact and Approximated Data-Reuse Optimizations for Tiling with Parametric Sizes

Darte

Isoard

2015

Lecture Notes in Computer Science

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Loop tiling is a loop transformation widely used to improve spatial and temporal data locality, to increase computation granularity, and to enable blocking algorithms, which are particularly useful when offloading kernels on computing units with smaller memories. When caches are not available or used, data transfers and local storage must be software-managed, and some useless remote communications can be avoided by exploiting data reuse between tiles. An important parameter of tiling is the sizes of the tiles, which impact the size of the required local memory. However, for most analyses involving several tiles, which is the case for inter-tile data reuse, the tile sizes induce non-linear constraints, unless they are numerical constants. This complicates or prevents a parametric analysis with polyhedral optimization techniques. This paper shows that, when tiles are executed in sequence along tile axes, the parametric (with respect to tile sizes) analysis for inter-tile data reuse is nevertheless possible, i.e., one can determine, at compile-time and in a parametric fashion, the copy-in and copy-out data sets for all tiles, with inter-tile reuse, as well as sizes for the induced local memories. When approximations of transfers are performed, the situation is much more complex, and involves a careful analysis to guarantee correctness when data are both read and written. We provide the mathematical foundations to make such approximations possible. Combined with hierarchical tiling, this result opens perspectives for the automatic generation of blocking algorithms, guided by parametric cost models, where blocks can be pipelined and/or can contain parallelism. Previous work on FPGAs and GPUs already showed the interest and feasibility of such automation with tiling, but in a non-parametric fashion.

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Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS tool

Cited by 6 publications

References 17 publications

Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA

Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA

Automatic Generation of FPGA-Specific Pipelined Accelerators

Exact and Approximated Data-Reuse Optimizations for Tiling with Parametric Sizes

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