Optimizing DSP circuits by a new family of arithmetic operators

Abstract

Abstract-A new family of arithmetic operators to optimize the implementation of circuits for digital signal processing is presented. Thanks to use of a new technique which reduces the quantification errors, the proposed operators may decrease significantly the size of the circuits required for most applications. That means a simultaneous reduction of area, delay and power consumption.

New Formats for Computing with Real-Numbers under Round-to-Nearest

“…In this section, we formalize and extend the ideas used in [6] to optimize digital signal processing data-paths. A new representation system is defined, which allows simplifying the computation of round-to-nearest rounding and radix complement.…”

“…On the other hand, in [6], we have presented the utilization of a new format for binary two's complement fixed-point representation to optimize the hardware implementation of digital filters. Similarly to the one in [5], this new representation system drastically simplifies the computation of round-to-nearest rounding and the two's complement operation.…”

“…Similarly to the one in [5], this new representation system drastically simplifies the computation of round-to-nearest rounding and the two's complement operation. Here, we formalize the new proposed format [6] and generalize it for different radices and sign representation. These new formats are based on shifting the numbers that can be exactly represented under conventional formats by adding a bias which equals half unit-inthe-last-place (ULP).…”

Floating Point Square Root under HUB Format

“…In [6] a half-precision floating-point HUB unit is used for high dynamic range image and video systems (based on additions and multiplications). By reducing bit-width while This work has been supported by the Ministry of Science and Innovation of Spain under project CICYT TIN2016-80920R maintaining the same accuracy, the area cost and delay of FIR filter implementations has been drastically reduced in [3], and similarly for the QR decomposition in [4].…”

“…The efficiency of using HUB for fixed-point representation has been showed in [3] and [4] and for floating-point in [5], [6] and [7] (HUB format is not valid for pure integer numbers). In [6] a half-precision floating-point HUB unit is used for high dynamic range image and video systems (based on additions and multiplications).…”