Optimizing FPGA-based hard networks-on-chip by minimizing and sharing resources

Attia, Sameh; Fahmy, Hossam A. H.; Ismail, Yehea; Mostafa, Hassan

doi:10.1016/j.vlsi.2018.06.005

Cited by 5 publications

(4 citation statements)

References 10 publications

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“…The topology, routing algorithm and its switching type are considered as the most important items in designing an NoC. The topology shows how the processing elements are connected (Attia et al, 2018). In other words, topology is a type of graph whose nodes are network processing elements and links are the connections between these elements.…”

Section: Network-on-chipmentioning

confidence: 99%

Reducing the number of passing links in the 2D-NoC for performance and reliability improvement

Chabok

Alavi

2020

WJE

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Purpose The routing algorithm is one of the most important components in designing a network-on-chip (NoC). An effective routing algorithm can cause better performance and throughput, and thus, have less latency, lower power consumption and high reliability. Considering the high scalability in networks and fault occurrence on links, the more the packet reaches the destination (i.e. to cross the number of fewer links), the less the loss of packets and information would be. Accordingly, the proposed algorithm is based on reducing the number of passed links to reach the destination. Design/methodology/approach This paper presents a high-performance NoC that increases telecommunication network reliability by passing fewer links to destination. A large NoC is divided into small districts with central routers. In such a system, routing in large routes is performed through these central routers district by district. Findings By reducing the number of links, the number of routers also decreases. As a result, the power consumption is reduced, the performance of the NoC is improved, and the probability of collision with a faulty link and network latency is decreased. Originality/value The simulation is performed using the Noxim simulator because of its ability to manage and inject faults. The proposed algorithm, XY routing, as a conventional algorithm for the NoC, was simulated in a 14 × 14 network size, as the typical network size in the recent works.

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Section: Network-on-chipmentioning

confidence: 99%

Reducing the number of passing links in the 2D-NoC for performance and reliability improvement

Chabok

Alavi

2020

WJE

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“…In fact, high‐power consumption and low‐operating frequency are side effects of FPGAs flexibility and reconfigurability. For synthesis and implementing routers and PEs of FPGA‐based NoCs, it is important to consider these limitations and characteristics of FPGAs 9‐30 …”

Section: Introductionmentioning

confidence: 99%

“…Hence, FPGA-based designs consume high energy, unless, their designers utilize techniques at algorithm, system, and circuit levels for diminishing power consumption. Several research works [18][19][20][21][22][23][24][25][26][27][28][29][30] have been done on analysis and reduction of the power consumption of FPGA-based NoCs. It is noticeable that in an FPGA-based NoC approximately 78%-85% of the power consumption is dynamic.…”

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confidence: 99%

A high‐performance FPGA‐based multicrossbar prioritized network‐on‐chip

Alaei

Yazdanpanah

2020

Concurrency and Computation

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High performance system-on-chip (SoCs) designs have led to high-density integrated circuits using field programmable gate arrays (FPGAs) for rapid prototyping and reconfigurable digital circuits. Using FPGA reconfigurability, it is possible to design a configurable network-on-chip (NoC) for different applications. NoC architectures provide efficient communication infrastructures for implementing very large SoCs. In this article, we propose HiFMP, a high-performance FPGA-based multicrossbar prioritized NoC router. The aim followed by the proposed router is designing a low-power NoC router with high performance in terms of energy-efficiency, network throughput, area, and latency for efficient FPGA realization. HiFMP is a parameterizable router, and is effectively used for an FPGA-based NoC with mesh topology. Performance evaluations include network-level analysis and hardware exploration; the results demonstrate the effectiveness and high performance of HiFMP in terms of latency, throughput, power consumption, and area, comparing with the existing related architectures. K E Y W O R D S FPGA, low-power design, multicrossbar, network-on-chip, priority-based router 1 INTRODUCTION In high-density emerging SoC architectures, there are a large number of processing elements (PEs) communicating through intensive on-chip interconnections that significantly affect different aspects of the performance. For large SoCs, point-to-point and bus-based interconnections do not provide efficient on-chip network infrastructures because of large amount of hardware, high latency, high power consumption, and/or complicated synchronization. NoCs, as high-performance architectures, arise to overcome the limitations of traditional on-chip structures. 1-5 NoCs provide high-performance and power scalable and modular interconnections. In addition, with NoC architectures, the system complexity is reduced by separating communication and computation units. A NoC includes routers, links, and network interfaces in order to prepare a network infrastructure for interconnecting PEs. Links of NoCs consist of physical channels (i.e., a group of wires), and optional virtual channels (VCs) as a set of additional buffers in routers. 4-7 The channel bit-width (the number of wires in a unidirectional channel) depends on the bandwidth requirements of the applications and available chip area. Generally, links of NoC have two physical unidirectional channels for fully duplexed communication, allowing data to flow both ways without collisions. 1 Routers are the most important modules of the communication backbone of NoC architectures. So, it is essential to design them with low latency, low power consumption, and high throughput. The router complexity and performance impacts the latency, power consumption, area, throughput, and the cost of on-chip networks. 8 Field programmable gate arrays (FPGAs) are flexible, easy-to-use, and cost effective reprogrammable devices with fast and simple design flow. FPGA designers generally do not need to care for clock distribut...

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“…[3] - [5]. Furthermore, the present FPGA's interconnection structure has several shortcomings that poorly affect the performance, limited the FPGA speed, and maximize the communication protocol [6].…”

Section: Introductionmentioning

confidence: 99%

An Adaptive Arbitration Technique w ith 4x4 Mesh Topology f or Low Area a nd High Speed NOC Design

Salagala*,

Sharma,

Laxmanarayana

2020

IJITEE

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 Abstract: In recent days, On-Chip Communication is a major requirement in modern systems that produce efficient communication with less complexity and high throughput. Due to heavy traffic and increasing Network-On Chip (NoC) size, the routing algorithm produces poor performances. Normally, round-robin and matrix arbiters are used in NoC for high-speed switches. In this research work, three different types of arbiter algorithms are used such as priority algorithm, Time Division Multiplexed (TDM) algorithm, and Viterbi algorithm to improve the linearity of the NOC. Initially, the priority algorithm helps to minimize traffic congestion when the arbiter is in a busy mode. Second, the fairness and Quality of Service (QoS) of the NoC structure are analyzed by the TDM algorithm. Finally, the Viterbi algorithm based error prediction process is done in an NoC structure. Due to the usage of three proposed arbiter algorithms, the area of NoC can be reduced. The packet can be reached to the destination by using the arbitration process with less loss. In this research, the proposed methodology is called as Low Area-Fault-Tolerant Adaptive Arbitration based NoC architecture (LA-FTAA-NoC architecture). Finally, the Field Programmable Gate Array (FPGA) performance is evaluated such as LUT, flip flop, slices, and frequency in Spartan 6 hardware. In the proposed method, 2.42% of LUT, 3.1% of flip flop, and 8.63% of slices have reduced when compared to existing work.

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Optimizing FPGA-based hard networks-on-chip by minimizing and sharing resources

Cited by 5 publications

References 10 publications

Reducing the number of passing links in the 2D-NoC for performance and reliability improvement

Reducing the number of passing links in the 2D-NoC for performance and reliability improvement

A high‐performance FPGA‐based multicrossbar prioritized network‐on‐chip

An Adaptive Arbitration Technique w ith 4x4 Mesh Topology f or Low Area a nd High Speed NOC Design

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