Optimizing Interconnect for Performance in Standard Cell Library

Shah, Dharin; Siva, Kothamasu; Girishankar, G.; Nagaraj, N.S.

doi:10.1109/apccas.2006.342397

Cited by 4 publications

(1 citation statement)

References 6 publications

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“…As far as the active devices are concerned, accurate process dependent transistor models including parasitics effects can be found in the literature. As for the minimization of the active devices variations, several techniques such as silicon strain and high-K gate dielectric, among others, have been proposed as a way of maintaining transistors performance in spite of the everdiminishing device sizes [7], the variability of the active devices parameters will not be considered in this paper. Yet the need for using integrated inductors raises additional modelling needs where the variability of the metal width, the spacing between conductor and the thickness of interlayer dielectrics must be taken into account.…”

Section: Fig 1 Lc-vco Design Architecturementioning

confidence: 99%

Optimization-Based Design of Nano-CMOS LC-VCOs

Pereira

Fino

Coito

et al. 2012

Technological Innovation for Value Creation

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Abstract. This paper introduces a variability-aware methodology for the design of LC-VCOs in Nano-CMOS technologies. The complexity of the design as well as the necessity for having an environment offering the possibility for exploring design trade-offs has led to the development of design methodologies based multi-objective optimization procedures yielding the generation of Pareto-optimal surfaces. The efficiency of the process is granted by using analytical models for both passive and active devices. Although physics-based analytical expressions have been proposed for the evaluation of the lumped elements, the variability of the process parameters is usually ignored due to the difficulty to formalize it into an optimization performance index. The usually adopted methodology of considering only optimum solutions for the Pareto surface, may lead to pruning quasi-optimal solutions that may prove to be better, should their sensitivity to process parameter variation be accounted for. In this work we propose starting by generating an extended Pareto surface where both optimum and quasi-optimum solutions are considered. Finally information on the sensitivity to process parameter variations, is used for electing the best design solution.

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Section: Fig 1 Lc-vco Design Architecturementioning

confidence: 99%