Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-core Processor

Salčić, Zoran; Nadeem, Muhammad; Park, Heejong; Teich, Jüergen

doi:10.1109/mcsoc.2016.34

2016 IEEE 10th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip (MCSOC) 2016

DOI: 10.1109/mcsoc.2016.34

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Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-core Processor

Zoran Salčić¹,

Muhammad Nadeem²,

Heejong Park³

et al.

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Noc-HMP

Salčić

Park

Teich

et al. 2017

ACM Trans. Des. Autom. Electron. Syst.

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Scalability and performance in multicore processors for embedded and real-time systems usually don't go well each with the other. Networks on Chip (NoCs) provide scalable execution platforms suitable for such kind of embedded systems. This article presents a NoC-based Heterogeneous Multi-Processor system, called NoC-HMP, which is a scalable platform for embedded systems developed in the GALS language SystemJ. NoC-HMP uses a time-predictable TDMA-MIN NoC to guarantee latencies and communication time between the two types of time-predictable cores and can be customized for a specific performance goal through the execution strategy and scheduling of SystemJ program deployed across multiple cores. Examples of different execution strategies are introduced, explored and analyzed via measurements. The number of used cores can be minimized to achieve the target performance of the application. TDMA-MIN allows easy extensions of NoC-HMP with other cores or IP blocks. Experiments show a significant improvement of performance over a single core system and demonstrate how the addition of cores affects the performance of the designed system.

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Noc-HMP

Salčić

Park

Teich

et al. 2017

ACM Trans. Des. Autom. Electron. Syst.

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show abstract

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Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-core Processor

Cited by 1 publication

References 10 publications

Noc-HMP

Noc-HMP

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