Optimizing Majority-Inverter Graphs With Functional Hashing

2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)

Haaswijk

et al. 2017

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Abstract-In this paper, we study exact multi-level logic benchmarks. We refer to an exact logic benchmark, or exact benchmark in short, as the optimal implementation of a given Boolean function, in terms of minimum number of logic levels and/or nodes. Exact benchmarks are of paramount importance to design automation because they allow engineers to test the efficiency of heuristic techniques used in practice. When dealing with two-level logic circuits, tools to generate exact benchmarks are available, e.g., espresso-exact, and scale up to relatively large size. However, when moving to modern multi-level logic circuits, the problem of deriving exact benchmarks is inherently more complex. Indeed, few solutions are known. In this paper, we present a scalable method to generate exact multi-level benchmarks with the optimum, or provably close to the optimum, number of logic levels. Our technique involves concepts from graph theory and joint support decomposition. Experimental results show an asymptotic exponential gap between state-ofthe-art synthesis techniques and our exact results. Our findings underline the need for strong new research in logic synthesis.

Section: B Resultsmentioning

confidence: 99%

“…In our context, we would look for depth-increasing transformations. Rewriting techniques [18], [26] can have their internal goal easily modified for this purpose. While this approach can be more scalable, the corresponding suboptimal circuits have weaker properties w.r.t.…”

Section: A Scalable Collapsingmentioning

confidence: 99%

Multi-level logic benchmarks: An exactness study

2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)

Haaswijk

et al. 2017

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“…For large arithmetic circuits, it has been shown that M n , n > 3 can be beneficial for compactness of the representation as well as the final implementation if a rich cell library is available [19], [1]. An improved bound for the MIG node count is presented recently in [23], where minimum MIG representations are precomputed for functions up to 4 variables. In the following section, heterogeneity in majority Boolean algebra is explored.…”

Section: Lemma 5 the Mig Representation Of An N-variablementioning

confidence: 99%

Notes on Majority Boolean Algebra

Chattopadhyay

2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)

et al. 2016

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Abstract-A Majority-Inverter Graph (MIG) is a homogeneous logic network, where each node represents the majority function. Recently, a logic optimization package based on the MIG datastructure, with 3-input majority node (M3) has been proposed [2], [30]. It is demonstrated to have efficient area-delay-power results compared to state-of-the-art logic optimization packages. In this paper, the Boolean algebraic transformations based on majority logic, i.e., majority Boolean algebra is studied. In the first part of this paper, we summarize a range of identities for majority Boolean algebra with their corresponding proofs. In the second part, we venture towards heterogeneous logic network and provide reversible logic mapping of majority nodes.

“…By precomputing size-optimum AIGs for a subclass of NPN classes of 5-variable functions, the area of highly optimized large networks may be reduced by 5.57% on average [12]. A similar method has recently been introduced for MIG size optimization [13].…”

Section: Introductionmentioning

confidence: 99%

A novel basis for logic rewriting

Haaswijk

2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)

et al. 2017

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Abstract-Given a set of logic primitives and a Boolean function, exact synthesis finds the optimum representation (e.g., depth or size) of the function in terms of the primitives. Due to its high computational complexity, the use of exact synthesis is limited to small networks. Some logic rewriting algorithms use exact synthesis to replace small subnetworks by their optimum representations. However, conventional approaches have two major drawbacks. First, their scalability is limited, as Boolean functions are enumerated to precompute their optimum representations. Second, the strategies used to replace subnetworks are not satisfactory. We show how the use of exact synthesis for logic rewriting can be improved. To this end, we propose a novel method that includes various improvements over conventional approaches: (i) we improve the subnetwork selection strategy, (ii) we show how enumeration can be avoided, allowing our method to scale to larger subnetworks, and (iii) we introduce XOR Majority Graphs (XMGs) as compact logic representations that make exact synthesis more efficient. We show a 45.8% geometric mean reduction (taken over size, depth, and switching activity), a 6.5% size reduction, and depth · size reductions of 8.6%, compared to the academic state-of-the-art. Finally, we outperform 3 over 9 of the best known size results for the EPFL benchmark suite, reducing size by up to 11.5% and depth up to 46.7%.