Optimizing message-passing on multicore architectures using hardware multi-threading

Abstract

Shared-memory and message-passing are two op- posite models to develop parallel computations. The shared- memory model, adopted by existing frameworks such as OpenMP, represents a de-facto standard on multi-/many-core architectures. However, message-passing deserves to be studied for its inherent properties in terms of portability and flexibility as well as for its better ease of debugging. Achieving good performance from the use of messages in shared-memory architectures requires an efficient implementation of the run-time support. This paper investigates the definition of a delegation mechanism on multi- threaded architectures able to: (i) overlap communications with calculation phases; (ii) parallelize distribution and collective oper- ations. Our ideas have been exemplified using two parallel bench- marks on the Intel Phi, showing that in these applications our message-passing support outperforms MPI and reaches similar performance compared to standard OpenMP implementations

The home-forwarding mechanism to reduce the cache coherence overhead in next-generation CMPs

“…[15] and used to synchronize and exchange messages between threads like in Ref. [38]. The mechanism provides a point-to-point communication between two partners, sender (S) and receiver (R), with a buffer of one position.…”

OMP2MPI: Automatic MPI code generation from OpenMP programs

“…MPI allows to communicate among cores on different nodes, and one could think that it introduces performance overheads at the node level compared with OpenMP. But this is a controversial issue with no clear answer as shown in [14,6].…”