Optimizing performance and yield of vertical GaN diodes using wafer scale optical techniques

Abstract

To improve the manufacturing of vertical GaN devices for power electronics applications, the effects of defects in GaN substrates need to be better understood. Many non-destructive techniques including photoluminescence, Raman spectroscopy and optical profilometry, can be used to detect defects in the substrate and epitaxial layers. Raman spectroscopy was used to identify points of high crystal stress and non-uniform conductivity in a substrate, while optical profilometry was used to identify bumps and pits in a substrate which could cause catastrophic device failures. The effect of the defects was studied using vertical P-i-N diodes with a single zone junction termination extention (JTE) edge termination and isolation, which were formed via nitrogen implantation. Diodes were fabricated on and off of sample abnormalities to study their effects. From electrical measurements, it was discovered that the devices could consistently block voltages over 1000 V (near the theoretical value of the epitaxial layer design), and the forward bias behavior could consistently produce on-resistance below 2 mΩ cm2, which is an excellent value considering DC biasing was used and no substrate thinning was performed. It was found that high crystal stress increased the probability of device failure from 6 to 20%, while an inhomogeneous carrier concentration had little effect on reverse bias behavior, and slightly (~ 3%) increased the on-resistance (Ron). Optical profilometry was able to detect regions of high surface roughness, bumps, and pits; in which, the majority of the defects detected were benign. However a large bump in the termination region of the JTE or a deep pit can induce a low voltage catastrophic failure, and increased crystal stress detected by the Raman correlated to the optical profilometry with associated surface topography.

Using machine learning with optical profilometry for GaN wafer screening

“…Third, the experiment contained thousands of samples, which is enough to see if there is a trend, but typically millions are required to train a model suitable for commercial manufacturing. Fourth, our previous research 33 has shown that many benign defects are present as shown by the cluster plots in Fig. 5 from the large number of points at approximately 0.1% outlier area and an RMS roughness of approximately 5 nm.…”

Deep-UV photoemission electron microscopy for imaging nanoscale heterogeneity and defects in gallium nitride

“…The GaN samples investigated were 500 nm thick p-type (Mg dopant) layers epitaxially grown via metal-organic chemical vapor deposition (MOCVD) on an 8 µm thick unintentionally doped (UID) buffer layer on an n-type GaN substrate 16,17 . The samples were coated in photoresist for transport.…”

“…Elimination of dislocations is crucial for device reliability, as dislocations in the substrate are known to propagate through the epitaxial growth, compromising the active device layers 11,12 . For example, substrates with patterned arrays of dislocation centers exhibit spatially-varying device performance and failure locations [13][14][15][16][17] . However, direct correlation between defective substrate areas, dislocations, and device performance is not straightforward: certain defects appear to be more harmful for devices than others 11,12,16,17 .…”

“…For example, substrates with patterned arrays of dislocation centers exhibit spatially-varying device performance and failure locations [13][14][15][16][17] . However, direct correlation between defective substrate areas, dislocations, and device performance is not straightforward: certain defects appear to be more harmful for devices than others 11,12,16,17 . Therefore, knowledge of the electronic properties of these defects, which propagate to the surface during the epitaxial growth, is needed to understand the device failure pathways.…”

Improving vertical GaN p–n diode performance with room temperature defect mitigation

“…As a result, lateral devices are limited to low-to medium-voltage applications (less than 1 kV). On the other hand, vertical geometry devices offer several advantages over lateral devices, such as better scaling factors and thermal management, a higher critical electric field and breakdown voltage, and better radiation tolerance [9,10]. Several studies have reported the attractive performance of vertical GaN-on-GaN p-n diodes, which have a high breakdown voltage (4-6 kV) [11][12][13] and low specific on-resistance (less than 0.5 mΩ cm 2 ) [10,14].…”