Optimizing pipelined networks of associative and commutative operators

Hartley, Richard; Casavant, Albert E.

doi:10.1109/43.329271

Cited by 21 publications

(6 citation statements)

References 14 publications

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“…Furthermore, the reductions are consistent. In summary, the comparisons of the results strongly suggest that considering layout effects 6 'optimal' when considering gate delays only. 7 The target layout we used is gate array (lattice) style for simplicity, but our approach can be applied to any layout style such as standard cell and FPGA.…”

Section: Resultsmentioning

confidence: 88%

Layout-aware synthesis of arithmetic circuits

Kim

2002

Proceedings of the 39th Conference on Design Automation - DAC '02

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In deep sub-micron (DSM) technology, wires are equally or more important than logic components since wire-related problems such as crosstalk, noise are much critical in system-on-chip (SoC) design. Recently, a method [12] for generating a partial product reduction tree (PPRT) with optimal-timing using bit-level adders to implement arithmetic circuits, which outperforms the current best designs, is proposed. However, in the conventional approaches including [12], interconnects are not primary components to be optimized in the synthesis of arithmetic circuits, mainly due to its high integration complexity or unpredictable wire effects, thereby resulting in unsatisfactory layout results with long and messed wire connections. To overcome the limitation, we propose a new module generation/synthesis algorithm for arithmetic circuits utilizing carry-save-adder (CSA) modules, which not only optimizes the circuit timing but also generates a much regular interconnect topology of the final circuits. Specifically, we propose a two-step algorithm: (Phase 1: CSA module generation) we propose an optimal-timing CSA module generation algorithm for an arithmetic expression under a general CSA timing model; (Phase 2: Bit-level interconnect refinements) we optimally refine the interconnects between the CSA modules while retaining the global CSA-tree structure produced by Phase 1. It is shown that the timing of the circuits produced by our approach is equal or almost close to that by [12] in most testcases (even without including the interconnect delay), and at the same time, the interconnects in layout are significantly short and regular.

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Section: Resultsmentioning

confidence: 88%

Layout-aware synthesis of arithmetic circuits

Kim

2002

Proceedings of the 39th Conference on Design Automation - DAC '02

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“…Algebraic optimization techniques have been employed for improving resource utilization [ 1 I], tree height minimization [4,5], maximization of data throughput [7][6] and minimization of power consumption [2] (see [ 111 for a comprehensive overview). Although all published approaches are very powerful in their own domain, most of them have certain restrictions concerning the set of supported transformation rules (commutativity, associativity, distributivity, and some special domain-specific rules are usually exploited) and the objective function to be optimized.…”

Section: Introductionmentioning

confidence: 99%

A genetic algorithm based approach for multi-objective data-flow graph optimization

Landwehr

1999

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)

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This paper presents a genetic algorithm based approach for algebraic optimization of behavioral system specifications. We introduce a chromosomal representation of data-flow graphs (DFG) which ensures that the correctness of algebraic transformations realized by the underlying genetic operators selection, recombination, and mutation is always preserved. We present substantial fitness functions for both the minimization of overall resource costs and critical path length. We also demonstrate that, due to their flexibility, genetic algorithms can be simply adapted to different objective functions which is examplarily shown for power optimization. In order to avoid inferior results caused by the counteracting demands on resources of different basic blocks, all DFGs of the input description are optimized concurrently.Experimental results for several standard benchmarks prove the efficiency of our approach.

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“…As a result, MCM techniques have evolved as the most efficient ones in realizing filter coefficients. Therefore, many efforts have been made to reduce the number of SA and MB adders within the MCM context [23][24][25][26][27][28]30,33,37,38,41,[43][44][45]54,[56][57][58][70][71][72]. Although most MCM algorithms are considered in transposed direct form, it should be noted that the direct form may synthesize the filter in the same complexity.…”

Section: Early Workmentioning

confidence: 99%

“…To avoid the extrapolation of the center coefficient being added twice in the implementation where coefficient symmetry is exploited, a modified structure, illustrated by a 10-th order example, is shown in Table 3.3: Impulse Response of Example 2. Coefficients from ℎ (13) to ℎ (25) are chosen as the prototype lobe. Residuals from ℎ (0) to ℎ (12) and coefficients from ℎ (13) to ℎ (31) are realized in the multiplier block.…”

Section: Examplementioning

confidence: 99%

Low power and low complexity digital filters design and implementation

Shi¹

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Impulse Response of Example 2. Coefficients from ℎ(13) to ℎ(25) are chosen as the prototype lobe. Residuals from ℎ (0) to ℎ (12) and coefficients from ℎ(13) to ℎ(31) are realized in the multiplier block. ℎ() = ℎ () + 0 ℎ(+ 13) for = 0, 1, ⋅ ⋅ ⋅ , 12, where 0 = −4.. . 3.4 Impulse Response of Example 1. Coefficients from ℎ(37) to ℎ(45) are chosen as the prototype lobe. Residuals from ℎ (1) to ℎ (36), coefficients ℎ(0) and ℎ(37) to ℎ(60) are realized in the multiplier block.

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Optimizing pipelined networks of associative and commutative operators

Cited by 21 publications

References 14 publications

Layout-aware synthesis of arithmetic circuits

Layout-aware synthesis of arithmetic circuits

A genetic algorithm based approach for multi-objective data-flow graph optimization

Low power and low complexity digital filters design and implementation

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