Optimizing post-silicon conformance checking

Abstract

Abstract-Virtual prototypes of hardware devices, a.k.a, virtual devices, are increasingly used to enable early software development before silicon prototypes/devices are available. In previous work, we presented a post-silicon conformance checking approach to detecting interface state inconsistencies between a silicon device and its virtual device. In this paper, we present an optimization, adaptive concretization, to reduce the overhead incurred by symbolic execution, a key technique used in our conformance checking approach. We have evaluated our optimized approach on three Ethernet adapters and their virtual devices. The results demonstrate that it is effective and efficient: 21 inconsistencies are discovered and time usages are reduced by an order of magnitude, comparing to the previous approach.

Automatic generation of high-coverage tests for RTL designs using software techniques and tools

“…For high-level synthesis, symbolic execution is used for executing both high-level C design and low-level RTL design symbolically and then equivalence checking is conducted. For post-silicon functional validation, symbolic execution of virtual devices has been employed to support test generation [11,27,28] and conformance checking [12,29,30].…”

A Survey of Virtual Prototyping Techniques for System Development and Validation

“…They have applied the approach to estimating coverage of some test suites on several virtual network devices. Furthermore, they have extended their approach to support coverage estimation and conformance checking on silicon devices in the post-silicon validation [11,25,26].…”