Optimizing U-Shape FinFETs for Sub-5nm Technology: Performance Analysis and Device-to-Circuit Evaluation in Digital and Analog/Radio Frequency Applications

Abstract

FinFET is considered a potential contender in the era of Multigate field-effect transistors (FETs). Here, we present structural variations for Junctionless FinFET devices at the IRDS sub-5nm technology node. Four JL-FinFET novel structures are proposed, JL-MG-U-FinFET, JL-U-FinFET, JL-Inv-U-FinFET, and JL-DG-Inv-U-FinFET. The electrical and analog/RF performance of these structures are compared and it is found that JL-DG-Inv-U-FinFET gives better performance in terms of minimizing short channel effects as well as in terms of analog/radio frequency characteristics. The ION/IOFF ratio values for (JL-MG-U-FinFET, JL-U-FinFET, JL-Inv-U-FinFET, and JL-DG-Inv-U-FinFET) are observed as 8.5×106, 1.2×109, 2.04×108, and 1.1×1010, respectively. Similarly, the SS values are noted as 93.44, 70.87, 70.61, and 62.1 mV/dec for the respective configurations. The effect of variation in geometrical parameters such as gate length, U-shaped fin width, and U-shaped fin height on DC and analog/RF characteristics is also explored. It has been observed that the DC parameters such as Ion/Ioff ratio, SS are better for higher Lg, lower WU-fin, and higher HU-fin. Moreover, the JL-DG-Inv-U-FinFET-based common source amplifier produced a gain of 5.2. The results reported will aid device engineers in selecting better geometrical parameters to achieve improved JL-DG-Inv-U-FinFET performance.

Pushing the Boundaries: Design and Simulation Approach of Negative Capacitance Nanosheet FETs with Ferroelectric and Dielectric Spacers at the Sub-3 nm Technology Node for Analog/RF/Mixed Signal Applications

“…The transconductance and minimizing g ds is pivotal to optimize device performance and overall circuit functionality. 35 The effect of g m and g ds on the proposed spacer configurations is indicated in Figure 4a. It is found that the g m is high for Source-FE Drain-DE and Both FE spacer configurations as compared to the other two configurations.…”

“…The output conductance ( g ds = ∂ I d ∂ V ds ) signifies the susceptibility of drain current to variations in drain-source voltage. Managing and minimizing g ds is pivotal to optimize device performance and overall circuit functionality . The effect of g m and g ds on the proposed spacer configurations is indicated in Figure a.…”

An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation

“…This section shows the circuit application of the proposed DMGC CGAA FET device. The common source (CS) amplifier plays a key role in analog integrated circuit applications [36,37]. Figure 9 shows the CS amplifier circuit with proposed device and the circuit elements are properly selected to operate the DMGC CGAA FET as an amplifier.…”

Optimization of Sidewall Spacer Engineering at Sub-5 nm Technology Node For JL-Nanowire FET: Digital/Analog/RF/Circuit Perspective

“…MGFETs are presented as a substitute to conventional FETs as they incorporate extra gates, resulting in enhanced drain potential screening. 6 Among multi-gate devices, dual-gate (DG) FETs are particularly preferable due to their lower parasitic capacitances 7 and resilient behaviour over random dopant variations. This has led to the emergence of FinFETs in the current technological era.…”