Optimum Wordlength Search Using Sensitivity Information

Abstract

Many digital signal processing algorithms are first developed in floating point and later converted into fixed point for digital hardware implementation. During this conversion, more than 50% of the design time may be spent for complex designs, and optimum wordlengths are searched by trading off hardware complexity for arithmetic precision at system outputs. We propose a fast algorithm for searching for an optimum wordlength. This algorithm uses sensitivity information of hardware complexity and system output error with respect to the signal wordlengths, while other approaches use only one of the two sensitivities. This paper presents various optimization methods, and compares sensitivity search methods. Wordlength design case studies for a wireless demodulator show that the proposed method can find an optimum solution in one fourth of the time that the local search method takes. In addition, the optimum wordlength searched by the proposed method yields 30% lower hardware implementation costs than the sequential search method in wireless demodulators. Case studies demonstrate the proposed method is robust for searching for the optimum wordlength in a nonconvex space. Table 1: Fixed-point conversion approaches for integer wordlength (IWL) and for fractional wordlength (FWL) determination. Analytical approach Statistical approach Range model for IWL Error model for FWL Range statistic for IWL Error statistic for FWL Wadekar [8] Constantinides [9] C m a r [ 10] C m a r [ 10] Stephenson [11] Shi [12] Kim [13] Kum [14] Nayak [15] --Shi [12]Table 2: Optimum wordlength search methods. Cost sensitivity Error sensitivity Nonsensitivity Local search [3] Sequential search [5] Exhaustive search [4] Evolutive search [6] Max-1 search [16] Branch and bound [3] -Preplanned search [5]Complexity-and-distortion measure search-proposed

Fine Grain Precision Scaling for Datapath Approximations in Digital Signal Processing Systems

“…The method presented in this chapter, which we call dynamic scaling by variance propagation (DS-VP), is compared against four conventional methods: 1) non-scaling by full simulation (NS-FS), which only finds one set of word lengths for the worst-case operating point, 2) coarse dynamic scaling by full simulation search (CS-FS), which finds multiple sets of word lengths by full simulation, but using a single word length for all variables in a set, 2) dynamic scaling by full simulation search (DS-FS), which finds optimal sets of word lengths using full simulation, and 4) dynamic scaling by efficient simulation search (DS-ES), which finds multiple sets of word lengths using the efficient simulation approach from [12]. Table 1 shows the sets of word lengths found by the different methods across different target BERs and corresponding input SNRs.…”

“…To find the optimal word lengths using an exhaustive search requires 3.6 hours. With the preplanned simulation method from [12], the number of trials can be significantly reduced. For example, if the search starts from {2,2,2,2}, and the optimal word length set is {4,3,3,2}, optimal word lengths can be obtained with only 4 simulations.…”

“…By contrast, our analysis method requires only about 2ms to find a set of word lengths for one operating point, which is 5,000 times faster than the time for one simulation trial. Considering that word length optimizations can take up to 50% of design time with conventional simulation-based approaches [12], this represents a significant improvement in productivity.…”

“…For example, Sung et al [11] add a signal-toquantization noise ratio (SQNR) block to quantify the finite word-length effects when the word-length in the implementation of the system changes. In [12], various word length search methods are summarized and compared. The efficiency of simulationbased methods is analyzed to determine the number of simulations needed to reach optimum word lengths.…”

Automated wordlength optimization framework for multi-source statistical interval-based analysis of nonlinear systems with control-flow structures

“…This objective can be imposed by different motivations, from achieving small-sized chips and devices to the necessity of fitting a large design in an FPGA with limited resources. [HE06] demonstrates that the use of cost as minimization function outperforms error-oriented approaches. In order to reduce the hardware cost many works use the summation of word-lengths as guiding metric [WBGM97, CRS + 99, CSPL01, CSL02, CFCNT04].…”