Optoelectronic/VLSI

Goossen, K.W.

doi:10.1109/6040.803446

Cited by 3 publications

(3 citation statements)

References 21 publications

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“…For example, parallel computing architectures require high-bandwidth data links between chips capable of transmitting, receiving and even switching data at aggregate data rates exceeding 1Tb/s. It has already been shown [12] that the figures given by the ITRS for electrical I/O are inadequate when calculating the number of I/O required while keeping the ratio of I/O to computational bandwidth (number of gates × clock frequency) constant. This is equally valid for board-to-board and chip-to-chip communication.…”

Section: Inter-chip Optical Interconnect Technologymentioning

confidence: 98%

Optical solutions for system-level interconnect

O’Connor

2004

Proceedings of the 2004 International Workshop on System Level Interconnect Prediction

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Throughput, power consumption, signal integrity, pin count and routing complexity are all increasingly important interconnect issues that the system designer must deal with. Recent advances in integrated optical devices may deliver alternative interconnect solutions enabling drastically enhanced performance. This paper begins by outlining some of the more pressing issues in interconnect design, and goes on to describe system-level optical interconnect for inter-and intra-chip applications. Inter-chip optical interconnect, now a relatively mature technology, can enable greater connectivity for parallel computing for example through the use of optical I/O pads and wavelength division multiplexing. Intra-chip optical interconnect, technologically challenging and requiring new design methods, is presented through a proposal for heterogeneous integration of a photonic "above-IC" layer followed by a design methodology for on-chip optical links. Design technology issues are highlighted and the paper concludes with examples of the use of optical links in clock distribution (with quantitative comparisons of dissipated power between electrical and optical clock distribution networks) and for novel network on chip architectures.

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Section: Inter-chip Optical Interconnect Technologymentioning

confidence: 98%

Optical solutions for system-level interconnect

O’Connor

2004

Proceedings of the 2004 International Workshop on System Level Interconnect Prediction

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“…Optical links within a chip or between chips have been demonstrated but have not progressed beyond laboratory research. See, for example, the work reported in [1]- [3]. As such, it is worth reviewing the question as to where the divide between conductive and optical digital data transmission lies.…”

Section: Introductionmentioning

confidence: 98%

“…This situation is ameliorated in favor of optics in those situations in which an array of lasers share a common bias circuit and an array of receiver TIAs and post amplifiers also have a common bias circuitry [10]. 3) In terms of propagation delay, it is generally agreed that optical links can have lower latency than electrical links even over a few millimeters propagation distance, depending on line cross section [11], [12]. (4) Optical interconnect density is competitive with off-chip interconnect density because waveguide cores can be of the order of the optical wavelength, high-contrast index waveguides can be close together because of low crosstalk, signal fan-out is achievable to some extent and the dimensions of directly modulated VCSEL, FP lasers and detector bare dies are of the order of -, with electrical pads, comparable in size to present solder interconnects [9], [10].…”

Section: Introductionmentioning

confidence: 99%

Chip-to-Chip Optoelectronics SOP on Organic Boards or Packages

Chang

Guidotti

Liu

et al. 2004

IEEE Trans. Adv. Packag.

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In this paper, we demonstrate compatibility of hybrid, large-scale integration of both active and passive devices and components onto standard printed wiring boards in order to address mixed signal system-on-package (SOP)-based systems and applications. Fabrication, integration and characterization of high density passive components are presented, which includes the first time fabrication on FR-4 boards of a polymer buffer layer with nano scale local smoothness, blazed polymer surface relief gratings recorded by incoherent illumination, arrays of polymer micro lenses, and embedded bare die commercial p-i-n photodetectors. These embedded optical components are the essential building blocks toward a highly integrated SOP technology. The effort in this research demonstrates the potential for merging high-performance optical functions with traditional digital and radio frequency (RF) electronics onto large area and low-cost manufacturing methodologies for multifunction applications.Index Terms-optical interconnections, optical planar waveguides.

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Flip-chip integration of selectively oxidized 850 nm VCSEL arrays

Geib

Choquette

Allerman

et al.

LEOS 2000. 2000 IEEE Annual Meeting Conference Proceedings. 13th Annual Meeting. IEEE Lasers and Electro-Optics Society 2000 An

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Combinations of dense rrumbers of high performance photonic and microelectronic devices originating from disparate technologies are needed to achieve the next generation of information processing, interconnect, and intelligcnt sensing microsystems. Previous flip-chip VCSELs bonded to microelectronic circuitry were accomplished as isolated individual VCSEL islands, and often emitted at longer wavelengths for emission through the GaAs substratc [ 1,2]. However, 850 nm VCSELs are the most mature commercial tcchnology, and high count/density 2-dimensional arrays are desired for emerging applications. We report the fabrication techniques for flip-chip integration of selectively oxidized 850 nm 8x8 individually addressable VCSEI, arrays.For robust integration of 2-dimensional 850 nm VCSEL arrays to microelectronics, there are three challenges to overcome: 1) reliable bonding; 2) mechanically stable packaging; and 3 ) through substrate light emission. To achieve robust bonding ofVCSELs to Si or 111-V elcctronic circuitry, we have developed a silver post flip-chip process after Goossen [ 3 ] . The selectively oxidized 2-dimensional VCSEL arrays are completely fabricated [4] anti tested prior lo flip-chipping. The top facet of the VCSEL mesas are coated with a Au fjlm, then a Ag post, and finally another thin Au layer to provide the bonding contact. l h e flip-chip test coupon has matching electrical interconnections which extend Au contact pads out beyond the periphery of the VCSEL array die as shown in Fig. 1. (Eventually this coupon will be replaced with an integrated circuit driver chip.) To ensure mechanical stability between the VCSEL die aild the underlying coupon we cmploy an unfilled Dexter epoxy for under fill that readily wicks from the edges into the -6pm gap under the -2x2 nim' VCSEL dic. As evident from the cross section electron microscope image in Fig. 2, the epoxy completely fills in without voids, and secures the die to the coupon before substrate removal.Finally, to enable 850nm emission we remove the optically absorbing GaAs substrate by wet chemical jet etching. A 100 nm thick AlAs layer is utilized as an etch stop to preserve the VCSEL epitaxial material. Flip-chipped VCSEL assemblies have been tested on a probe station, as depicted in the inset of Fig. 3. l h e representative performance of a flip-chipped bottom emitting 850nm VCSEL with an oxide aperture of 14x14 pm2 is shown in Fig. 3 . We will also report on cfforts to improve uniformity and yield, as well as the performance of fully packaged flip-chipped VCSEL arrays. Rcfereticcs[I] U.

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Optoelectronic/VLSI

Cited by 3 publications

References 21 publications

Optical solutions for system-level interconnect

Optical solutions for system-level interconnect

Chip-to-Chip Optoelectronics SOP on Organic Boards or Packages

Flip-chip integration of selectively oxidized 850 nm VCSEL arrays

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