Orchestrating the execution of stream programs on multicore platforms

KudlurManjunath,; MahlkeScott,

doi:10.1145/1379022.1375596

Cited by 86 publications

(117 citation statements)

References 28 publications

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“…The stream programming models have been proven to be useful for programming stream architectures [7,12,29]. Some other research results also demonstrate their usefulness for general-purpose architectures [10,11,15].…”

Section: Introductionmentioning

confidence: 87%

Optimizing modulo scheduling to achieve reuse and concurrency for stream processors

2010

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Both reuse and concurrency are performance-critical for stream processors. When applying loop unrolling and software pipelining separately to streamlevel loops, either reuse or concurrency or both may be inadequately exploited. In this paper, we optimize modulo scheduling to maximize stream reuse and improve concurrency for stream-level loops. The key insight is that an unrolled and softwarepipelined stream-level loop could be described by a set of reuse equations. Guided by reuse equations, a reuse-aware modulo scheduling algorithm is developed to simultaneously optimize the two performance objectives, reuse, and concurrency, for a loop in a unified framework. Moreover, we describe a code generation algorithm to automatically produce the optimized loop from a given loop. The experimental results obtained on FT64 and by simulation demonstrate the effectiveness of the proposed approach.

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Section: Introductionmentioning

confidence: 87%

Optimizing modulo scheduling to achieve reuse and concurrency for stream processors

2010

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“…More recent work in homogeneous design time partitioning of streaming applications can be found in Gordon [2], Lin [9], Kudlur and Mahlke [10], Wei [11], and Wang [12].…”

Section: R E L At E D W O R Kmentioning

confidence: 99%

A communication model and partitioning algorithm for streaming applications for an embedded MPSoC

Kelly

Flasskamp

Sievers

et al. 2014

2014 International Symposium on System-on-Chip (SoC)

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Energy efficient embedded computing enables new application scenarios in mobile devices like software-defined radio and video processing. The hierarchical multiprocessor considered in this work may contain dozens or hundreds of resource efficient VLIW CPUs. Programming this number of CPU cores is a complex task requiring compiler support. The stream programming paradigm provides beneficial properties that help to support automatic partitioning. This work describes a compiler for streaming applications targeting the self-build hierarchical CoreVA-MPSoC multiprocessor platform. The compiler is supported by a programming model that is tailored to fit the streaming programming paradigm. We present a novel simulatedannealing (SA) based partitioning algorithm, called Smart SA. The overall speedup of Smart SA is 12.84 for an MPSoC with 16 CPU cores compared to a single CPU implementation. Comparison with a state of the art partitioning algorithm shows an average performance improvement of 34.07%. I . I N T R O D U C T I O NThe decreasing feature size of microelectronic circuits allows for the integration of more and more processing cores on a single chip. A Multiprocessor System-on-Chip (MPSoC) may consist of dozens of processing elements as CPU cores or specialized hardware accelerators connected by a highspeed communication infrastructure, i.e. a Network-On-Chip (NoC). However, mapping general purpose applications to a large number of MPSoC processing elements remains a nontrivial task. Manually writing low-level code for each core makes it difficult to experiment with different decompositions and mappings of computation to processors. Alternatively, higher-level programming frameworks allow the compiler to evaluate a larger design-space when mapping the application to different hardware configurations. Efficient mapping algorithms are important for finding optimized solutions. The Streaming paradigm provides regular and repeating computation and independent filters with explicit communication. This allows compilers to exploit the task more easily, data and pipeline parallelism commonly found in signal processing, multimedia, network processing, cryptology and similar application domains.A popular stream based programming language is StreamIt [1], [2]. The key principle of this language is to provide information about inherent parallelism of the program by using a structured data flow graph. This graph consisting of filters, pipelines, split-joins, and feedback loops.In this paper we present a compiler for the StreamIt Language targeting the self-build CoreVA-MPSoC architecture. The CoreVA-MPSoC is a highly scalable multiprocessor system based on a hierarchical communication infrastructure and the configurable VLIW 1 processor CoreVA.This paper is organized as follows: Section II describes our CoreVA-MPSoC hardware architecture. In Section III we discuss our StreamIt compiler with a focus on our novel simulated annealing partitioning algorithm (Smart SA). The communication model proposed in this work is presented in S...

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“…Software pipelining is then implemented to balance the load on different processors. In [16], an integer linear programming formulation is presented to select the optimal amount of partial expansion to generate balanced pipelined stages. One expansion solution is then passed to a heuristic that schedules the order of execution of instances to processors in order to reduce the application latency.…”

Section: Related Workmentioning

confidence: 99%

Partial expansion of dataflow graphs for resource-aware scheduling of multicore signal processing systems

Zaki

Plishker

Bhattacharyya

et al. 2014

2014 48th Asilomar Conference on Signals, Systems and Computers

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The complex design spaces associated with state-of-the-art, multicore signal processing systems pose significant challenges in realizing designs with high productivity and quality. The Partial Expansion Graph (PEG) implementation model was developed to help address these challenges by enabling more efficient exploration of the scheduling design space for multicore digital signal processors. The PEG allows designers and design tools to systematically adjust and adapt the amount of parallelism exposed from applications depending on the targeted platform. In this paper, we develop new algorithms for scheduling and mapping systems implemented using PEGs. Collectively, these algorithms operate in three steps. First, the amount of data parallelism in the application graph is tuned systematically over many iterations to profit from the available cores in the target platform. Then a mapping algorithm that uses graph analysis is developed to distribute data and task parallel instances over different cores while trying to balance the load of all processing units to make use of pipeline parallelism. Finally, we use a novel technique for performance evaluation by implementing the scheduler and a customizable solution on the programmable platform. We demonstrate the utility of our PEG-based scheduling and mapping algorithms through experiments on real application models and various synthetic graphs.

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Orchestrating the execution of stream programs on multicore platforms

Cited by 86 publications

References 28 publications

Optimizing modulo scheduling to achieve reuse and concurrency for stream processors

Optimizing modulo scheduling to achieve reuse and concurrency for stream processors

A communication model and partitioning algorithm for streaming applications for an embedded MPSoC

Partial expansion of dataflow graphs for resource-aware scheduling of multicore signal processing systems

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