Ordered escape routing based on Boolean satisfiability

Luo, Lijuan; Wong, D.F.

doi:10.1109/aspdac.2008.4483950

Cited by 10 publications

(3 citation statements)

References 14 publications

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“…SER deals with escape routing for two BGAs, requiring consistent ordering of escaped routes. Previous works have proposed various methods to solve these problems, including network flow models [12], [13] for UER problem, Boolean satisfiability (SAT) formulations [14] for OER, and boundary routing-based approaches [15] to solve the SER problem.…”

Section: Background and Related Workmentioning

confidence: 99%

A Pad-focused PCB Routing Algorithm Using Polygon-based Dynamic Partitioning

He,

Li,

Luo

et al. 2024

IEEE Access

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Routing plays a pivotal role in the design of printed circuit boards (PCBs). Existing automated routers typically tackle the routing problem by dividing it into two separate phases: escape routing and area routing. However, this approach often leads to suboptimal solutions or even the absence of solutions when transitioning from escape routing to area routing. In this paper, we propose a novel pad-focused, net-by-net, two-stage PCB routing approach comprising of a Monte Carlo tree search (MCTS)-based global routing stage, followed by an A*-based detailed routing stage. To bridge the gap between the global and detailed routing stages, we introduce a polygon-based dynamic routable region partitioning mechanism, ensuring that a detailed routing solution exists when a global routing solution is present. Experimental results demonstrate that our approach outperforms state-of-the-art routers in terms of the success rate and total wirelength on the test set. INDEX TERMS Area routing, Detailed routing, Escape routing, Global routing, Monte Carlo tree search, Printed circuit board

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Section: Background and Related Workmentioning

confidence: 99%

A Pad-focused PCB Routing Algorithm Using Polygon-based Dynamic Partitioning

He,

Li,

Luo

et al. 2024

IEEE Access

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“…Yan et al [6] presented a network model that accurately reflects routing resource capacity, resulting in improved results for unordered escape routing. Yan and Wong [7] introduced a network flow model for UER and modeled OER using Boolean satisfiability (SAT) formulas [8], [9]. The UER model is not suitable for practical applications involving designs with two or more components since the escape order between two components is often inconsistent, resulting in lower reliability of region routing.…”

Section: A Escape Routing and Region Routingmentioning

confidence: 99%

Unet-Astar: A Deep Learning-Based Fast Routing Algorithm for Unified PCB Routing

Yin,

Jin,

Chen

et al. 2023

IEEE Access

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In recent years, there has been extensive research on the routing problem of printed circuit boards (PCBs). Due to the increasing number of pins, high pin density, and unique physical constraints, manual PCB routing has become a time-consuming task to achieve design convergence. Previous work decomposed the problem into escape routing and area routing, focusing on these problems separately. However, there was always a gap between these two problems, requiring significant human effort for iterative algorithm adjustments. Furthermore, previous area routing work mainly focused on routing between ball grid array (BGA) packages in escape routing. However, in practice, many components are not in the form of BGA packages, such as passive devices, decoupling capacitors, and through-hole pin arrays. Therefore, it is necessary to study a unified routing approach. The current unified routing approach adopts the A* algorithm, but there is still room for improvement in routing speed. This paper proposes a new algorithm called Unet-Astar, which accelerates the routing efficiency by employing deep learning algorithms in a simulated environment. Additionally, a Deeper Unet is proposed for generating recommended regions for the routing algorithm. The new network structure can provide more contextual information, thereby improving routing efficiency. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm. Specifically, for all given test cases, our router achieves approximately a 70% improvement in runtime speed compared to the old router. Another major contribution of this work is the development of a routing problem set generator, which can generate parameterized routing problem sets with different sizes and constraints. This enables the evaluation of different routing algorithms and the generation of training datasets for future data-driven routing methods. All the code has been open-sourced and can be found at https://github.com/Firesuiry/Unet-Astar-For-PCB-Routing. INDEX TERMS physical design, printed circuit board, routing, Machine learning I. INTRODUCTION 1 This article has been accepted for publication in IEEE Access.

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“…Luo and Wang proposed that the OER problem could be modeled as a planar Boolean satisfiability problem [15] and that the problem could be solved using an existing Boolean satisfiability solver. However, this does not solve the capacity limitation problem.…”

Section: Introductionmentioning

confidence: 99%

Legalized Routing Algorithm Based on Linear Programming

Chen,

Tong,

Liu

et al. 2023

Electronics

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Legalized routing is an essential part of PCB automatic routing. It solves the problem of wiring conflicts and obtains routing results that comply with the constraints of design rules. Traditional legalized routing problems mostly use trial backtracking methods, but with increasing design complexity and design rules, avoiding wiring conflicts between networks has become increasingly challenging. This paper proposes a legalized routing algorithm based on linear programming to obtain the optimal wiring trajectory under specified topological constraints. First, the corresponding routing model was established based on numerous routing rules, and a routing grid diagram was found using obstacles as grid points. Secondly, a global routing algorithm was used to obtain the estimated wiring path, and integer linear programming was used to realize the mathematical modeling of the legalized routing problem. Finally, a multi-line simultaneous routing strategy was used to design and implement a detailed routing algorithm, optimizing the routing results. We use C++ to complete the coding work and thoroughly test the PCB use cases of different sizes. The experimental results show that our algorithm still maintains a 100% routing success rate, good time performance, and excellent routing quality with large-scale use cases compared with the trial backtracking method.

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Ordered escape routing based on Boolean satisfiability

Cited by 10 publications

References 14 publications

A Pad-focused PCB Routing Algorithm Using Polygon-based Dynamic Partitioning

A Pad-focused PCB Routing Algorithm Using Polygon-based Dynamic Partitioning

Unet-Astar: A Deep Learning-Based Fast Routing Algorithm for Unified PCB Routing

Legalized Routing Algorithm Based on Linear Programming

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