2010
DOI: 10.1103/physrevb.82.085302
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Origin of the bias stress instability in single-crystal organic field-effect transistors

Abstract: We report a systematic study of the bias stress effect at semiconductor-dielectric interfaces using singlecrystal organic field-effect transistors as a test bed. A combination of electrical transport and ultraviolet photoelectron spectroscopy suggests that this instability is due to a ground-state ͑i.e., occurring in the dark͒ charge transfer of holes from the accumulation channel of the semiconductor to localized states of a disordered insulator. The proposed model is not semiconductor specific and therefore … Show more

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Cited by 82 publications
(96 citation statements)
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“…We found severe carrier trapping for both electron and hole injection, indicative of bias stress: the trapping of injected charges, likely to occur at the semiconductor/dielectric interface. [28][29][30] Bias stress results in many trapped charges sceening the applied electric field, and a subsequent shift in the threshold voltage as a function of time. 24 The manifestation of trapping in the IR measurements, where repeated voltage applications are necessary, is discussed later.…”
Section: Resultsmentioning
confidence: 99%
“…We found severe carrier trapping for both electron and hole injection, indicative of bias stress: the trapping of injected charges, likely to occur at the semiconductor/dielectric interface. [28][29][30] Bias stress results in many trapped charges sceening the applied electric field, and a subsequent shift in the threshold voltage as a function of time. 24 The manifestation of trapping in the IR measurements, where repeated voltage applications are necessary, is discussed later.…”
Section: Resultsmentioning
confidence: 99%
“…1. The trend of a decreasing relaxation time with increasing HOMO energy was recently also found by Lee et al 13 A quantitative analysis is presented below.…”
mentioning
confidence: 90%
“…It was observed that the physical and chemical nature of the dielectric/organic interface plays a major role in determining the magnitude this effect 10,11 , but the precise microscopic origin of the phenomenon has remained elusive. Two possible mechanisms have been proposed for p-channel (hole accumulation) devices: one scenario attributes the effect to holes that are transferred from the FET channel to localized states in the gate insulator 11 ; another scenario invokes hole-assisted generation of protons in the presence of water, with the protons subsequently diffusing into the gate dielectric 10 . Both mechanisms lead to the accumulation of 3 positive charge (protons or holes) in the dielectric, which screens the external applied gate voltage, resulting in a reduction of the source-drain current.…”
mentioning
confidence: 99%