OS-Based NUMA Optimization: Tackling the Case of Truly Multi-thread Applications with Non-partitioned Virtual Page Accesses

Abstract

A common approach to improve memory access in NUMA machines exploits operating system (OS) page protection mechanisms to induce faults to determine which pages are accessed by what thread, so as to move the thread and its working-set of pages to the same NUMA node. However, existing proposals do not fully fit the requirements of truly multi-thread applications with non-partitioned accesses to virtual pages. In fact, these proposals exploit (induced) faults on a same page-table for all the threads of a same process to determine the access pattern. Hence, the fault by one thread (and the consequent re-opening of the access to the corresponding page) would mask those by other threads on the same page. This may lead to inaccuracy in the estimation of the working-set of individual threads. We overcome this drawback by presenting a lightweight operating system support for Linux, referred to as multi-view address space, explicitly targeting accuracy of per-thread working-set estimation in truly multi-thread applications with non-partitioned accesses, and an associated thread/data migration policy. Our solution is fully transparent to user-space code. It is embedded in a Linux/x86_64 module that installs any required modification to the original kernel image by solely relying on dynamic patching. A motivated case study in the context of HPC is also presented for an assessment of our proposal

Memory‐aware kernel mechanism and policies for improving internode load balancing on NUMA systems

“…Due to resource contention and the asymmetric access time for cores to access memory on remote nodes and the local node, researchers have developed various strategies for dealing with these issues to support NUMA systems. Some focus on the memory placement and data mapping policies that try to allocate memory or migrate pages for a process on the node for improving locality or balancing of memory access. To minimize remote memory access, memory access behaviors are detected, and pages are placed on the node with the most accesses to them.…”

“…To minimize remote memory access, memory access behaviors are detected, and pages are placed on the node with the most accesses to them. Some focus on sharing‐aware mapping, which maps threads accessing shared data to cores close to one another in the memory hierarchy and maps the data they accessed to their NUMA nodes. Some detect the memory access pattern for thread and data mapping on the hardware level, whereas some studies gather information from page faults or using a memory tracer tool.…”

“…To reduce remote memory access and/or resource contention, existing studies use various strategies. Most of them focus on either the scheduling techniques and thread mapping strategies or memory placement and data mapping policies.…”

“…There are many related studies on the issues of thread mapping and data mapping to NUMA nodes, and their strategies substantially improve performance and energy efficiency. However, lacking the consideration of an OS kernel's internode load‐balancing activity will reduce the effect on performance improvement.…”

“…This paper develops a kernel mechanism and policies to select suitable tasks for internode load balancing, with the purpose of reducing remote memory access incurred by task migration between nodes. Our approach differs from those in other studies, which detect memory access behaviors of processes from page faults and then map thread or data to nodes to improve memory affinity. We base on the memory usage information of tasks on each node and propose the kernel‐level memory‐aware load balancing (kMLB) mechanism to improve the Linux kernel's load balancing mechanism on NUMA systems.…”